Changeset 45ba9cf in mainline


Ignore:
Timestamp:
2006-01-08T12:03:41Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
2fe2046c
Parents:
8ccec3c1
Message:

Minor changes.

Files:
3 edited

Legend:

Unmodified
Added
Removed
  • doc/arch/amd64

    r8ccec3c1 r45ba9cf  
    2323
    2424EMULATORS AND VIRTUALIZERS
    25         o Bochs 2.2.1
     25        o Bochs 2.2.5
    2626        o Simics 2.2.19
  • doc/arch/ia32

    r8ccec3c1 r45ba9cf  
    1717
    1818SMP COMPATIBILITY
    19         o Bochs 2.0.2 - Bochs 2.2.1
     19        o Bochs 2.0.2 - Bochs 2.2.5
    2020                o 2x-8x 686 CPU
    2121        o Simics 2.0.28 - Simics 2.2.19
     
    3131
    3232EMULATORS AND VIRTUALIZERS
    33         o Bochs 2.0.2 - Bochs 2.2.1
     33        o Bochs 2.0.2 - Bochs 2.2.5
    3434        o VMware Workstation 4, VMware Workstation 5, VMware Workstation 5.5
    3535        o Simics 2.2.19
  • generic/include/cpu.h

    r8ccec3c1 r45ba9cf  
    4242#define CPU_STACK_SIZE  STACK_SIZE
    4343
     44/** CPU structure.
     45 *
     46 * There is one structure like this for every processor.
     47 */
    4448struct cpu {
    4549        SPINLOCK_DECLARE(lock);
     50
    4651        context_t saved_context;
    4752
     
    5863        #endif /* CONFIG_SMP */
    5964
     65        /**
     66         * Processor ID assigned by kernel.
     67         */
    6068        int id;
     69       
    6170        int active;
    6271        int tlb_active;
     
    6978        thread_t *fpu_owner;
    7079       
     80        /**
     81         * Stack used by scheduler when there is no running thread.
     82         */
    7183        __u8 *stack;
    7284};
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