Changeset 45ba9cf in mainline
- Timestamp:
- 2006-01-08T12:03:41Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 2fe2046c
- Parents:
- 8ccec3c1
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/arch/amd64
r8ccec3c1 r45ba9cf 23 23 24 24 EMULATORS AND VIRTUALIZERS 25 o Bochs 2.2. 125 o Bochs 2.2.5 26 26 o Simics 2.2.19 -
doc/arch/ia32
r8ccec3c1 r45ba9cf 17 17 18 18 SMP COMPATIBILITY 19 o Bochs 2.0.2 - Bochs 2.2. 119 o Bochs 2.0.2 - Bochs 2.2.5 20 20 o 2x-8x 686 CPU 21 21 o Simics 2.0.28 - Simics 2.2.19 … … 31 31 32 32 EMULATORS AND VIRTUALIZERS 33 o Bochs 2.0.2 - Bochs 2.2. 133 o Bochs 2.0.2 - Bochs 2.2.5 34 34 o VMware Workstation 4, VMware Workstation 5, VMware Workstation 5.5 35 35 o Simics 2.2.19 -
generic/include/cpu.h
r8ccec3c1 r45ba9cf 42 42 #define CPU_STACK_SIZE STACK_SIZE 43 43 44 /** CPU structure. 45 * 46 * There is one structure like this for every processor. 47 */ 44 48 struct cpu { 45 49 SPINLOCK_DECLARE(lock); 50 46 51 context_t saved_context; 47 52 … … 58 63 #endif /* CONFIG_SMP */ 59 64 65 /** 66 * Processor ID assigned by kernel. 67 */ 60 68 int id; 69 61 70 int active; 62 71 int tlb_active; … … 69 78 thread_t *fpu_owner; 70 79 80 /** 81 * Stack used by scheduler when there is no running thread. 82 */ 71 83 __u8 *stack; 72 84 };
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