Changes in kernel/arch/arm32/src/cpu/cpu.c [65871bb:46a6a5d] in mainline
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kernel/arch/arm32/src/cpu/cpu.c
r65871bb r46a6a5d 98 98 void cpu_arch_init(void) 99 99 { 100 #if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)101 100 uint32_t control_reg = 0; 102 101 asm volatile ( … … 105 104 ); 106 105 107 /* Turn off tex remap, RAZ ignores writesprior to armv7 */106 /* Turn off tex remap, RAZ/WI prior to armv7 */ 108 107 control_reg &= ~CP15_R1_TEX_REMAP_EN; 109 /* Turn off accessed flag, RAZ ignores writesprior to armv7 */108 /* Turn off accessed flag, RAZ/WI prior to armv7 */ 110 109 control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN); 111 /* Enable unaligned access, RAZ ignores writes prior to armv6 112 * switchable on armv6, RAO ignores writes on armv7, 110 /* Enable branch prediction RAZ/WI if not supported */ 111 control_reg |= CP15_R1_BRANCH_PREDICT_EN; 112 113 /* Unaligned access is supported on armv6+ */ 114 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6) 115 /* Enable unaligned access, RAZ/WI prior to armv6 116 * switchable on armv6, RAO/WI writes on armv7, 113 117 * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition 114 118 * L.3.1 (p. 2456) */ … … 124 128 * ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition 125 129 * B3.11.1 (p. 1383) 126 * ICache coherency is elaborate on in barrier.h.127 * We are safe to turn these on.130 * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469) 131 * L2 Cache for armv7 was enabled in boot code. 128 132 */ 129 control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN; 133 control_reg |= CP15_R1_CACHE_EN; 134 #endif 135 #ifdef PROCESSOR_cortex_a8 136 /* ICache coherency is elaborate on in barrier.h. 137 * Cortex-A8 implements IVIPT extension. 138 * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */ 139 control_reg |= CP15_R1_INST_CACHE_EN; 140 #endif 130 141 131 142 asm volatile ( … … 133 144 :: [control_reg] "r" (control_reg) 134 145 ); 135 #endif136 146 #ifdef CONFIG_FPU 137 147 fpu_setup();
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