Changes in uspace/drv/bus/pci/pciintel/pci.c [6dbc500:46eb2c4] in mainline

File:

• uspace/drv/bus/pci/pciintel/pci.c (modified) (7 diffs)

uspace/drv/bus/pci/pciintel/pci.c

@@ -256 +256 @@
         fibril_mutex_lock(&bus->conf_mutex);
 
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
 
         /*
@@ -263 +263 @@
          * support shorter PIO reads offset from this register.
          */
-        val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+        val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
 
         switch (len) {
@@ -299 +299 @@
                  * missing bits first.
                  */
-                pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-                val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
+                pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+                val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
         }
         
@@ -317 +317 @@
         }
 
-        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
-        pio_write_32(bus->conf_data_port, host2uint32_t_le(val));
+        pio_write_32(bus->conf_addr_reg, host2uint32_t_le(conf_addr));
+        pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
         
         fibril_mutex_unlock(&bus->conf_mutex);
@@ -449 +449 @@
                 hw_resources[count].res.io_range.address = range_addr;
                 hw_resources[count].res.io_range.size = range_size;
+                hw_resources[count].res.io_range.relative = true;
                 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
         } else {
@@ -454 +455 @@
                 hw_resources[count].res.mem_range.address = range_addr;
                 hw_resources[count].res.mem_range.size = range_size;
+                hw_resources[count].res.mem_range.relative = false;
                 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
         }
@@ -722 +724 @@
             hw_resources.resources[1].res.io_range.address);
         
-        bus->conf_io_addr =
-            (uint32_t) hw_resources.resources[0].res.io_range.address;
-        bus->conf_io_data =
-            (uint32_t) hw_resources.resources[1].res.io_range.address;
-        
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
-            &bus->conf_addr_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[0],
+            (void **) &bus->conf_addr_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;
                 goto fail;
         }
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
-            &bus->conf_data_port)) {
+        if (pio_enable_resource(&bus->pio_win, &hw_resources.resources[1],
+            (void **) &bus->conf_data_reg)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
                 rc = EADDRNOTAVAIL;