Changes in kernel/arch/amd64/src/smp/ap.S [9d58539:4928165] in mainline

File:

• kernel/arch/amd64/src/smp/ap.S (modified) (8 diffs)

kernel/arch/amd64/src/smp/ap.S

@@ -32 +32 @@
 #
 
+#include <abi/asmtool.h>
 #include <arch/boot/boot.h>
 #include <arch/boot/memmap.h>
@@ -38 +39 @@
 #include <arch/cpu.h>
 #include <arch/cpuid.h>
+#include <arch/context_struct.h>
 
 .section K_TEXT_START, "ax"
 
 #ifdef CONFIG_SMP
-
-.global unmapped_ap_boot
 
 # This piece of code is real-mode and is meant to be alligned at 4K boundary.
@@ -50 +50 @@
 
 .align 4096
-unmapped_ap_boot:
+SYMBOL(unmapped_ap_boot)
 .code16
         cli
@@ -59 +59 @@
         
         movl %cr0, %eax
-        orl $1, %eax
+        orl $CR0_PE, %eax
         movl %eax, %cr0     # switch to protected mode
         jmpl $GDT_SELECTOR(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET
@@ -76 +76 @@
         
         movl %cr4, %eax
-        btsl $5, %eax
+        orl $CR4_PAE, %eax
         movl %eax, %cr4
         
@@ -83 +83 @@
         
         # Enable long mode
-        movl $EFER_MSR_NUM, %ecx  # EFER MSR number
+        movl $AMD_MSR_EFER, %ecx  # EFER MSR number
         rdmsr                     # Read EFER
-        btsl $AMD_LME_FLAG, %eax  # Set LME=1
+        orl $AMD_LME, %eax        # Set LME=1
         wrmsr                     # Write EFER
         
         # Enable paging to activate long mode (set CR0.PG = 1)
         movl %cr0, %eax
-        btsl $31, %eax
+        orl $CR0_PG, %eax
         movl %eax, %cr0
         
@@ -99 +99 @@
 start64:
         movabsq $ctx, %rsp
-        movq (%rsp), %rsp
+        movq CONTEXT_OFFSET_SP(%rsp), %rsp
         
         pushq $0
@@ -113 +113 @@
 #ifdef CONFIG_SMP
 
-.global unmapped_ap_gdtr
-unmapped_ap_gdtr:
+SYMBOL(unmapped_ap_gdtr)
         .word 0
         .long 0