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  • kernel/arch/arm32/src/cpu/cpu.c

    r8316547f r49a736e2  
    9797}
    9898
    99 /** Enables unaligned access and caching for armv6+ */
     99/** Does nothing on ARM. */
    100100void cpu_arch_init(void)
    101101{
    102 #if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
     102#if defined(PROCESSOR_armv7_a)
    103103        uint32_t control_reg = 0;
    104104        asm volatile (
    … …  
    107107        );
    108108       
    109         /* Turn off tex remap, RAZ ignores writes prior to armv7 */
    110         control_reg &= ~CP15_R1_TEX_REMAP_EN;
    111         /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
    112         control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
    113         /* Enable unaligned access, RAZ ignores writes prior to armv6
    114          * switchable on armv6, RAO ignores writes on armv7,
    115          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    116          * L.3.1 (p. 2456) */
    117         control_reg |= CP15_R1_UNALIGNED_EN;
    118         /* Disable alignment checks, this turns unaligned access to undefined,
    119          * unless U bit is set. */
    120         control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
    121         /* Enable caching, On arm prior to armv7 there is only one level
    122          * of caches. Data cache is coherent.
    123          * "This means that the behavior of accesses from the same observer to
    124          * different VAs, that are translated to the same PA
    125          * with the same memory attributes, is fully coherent."
    126          *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
    127          *    B3.11.1 (p. 1383)
    128          * ICache coherency is elaborate on in barrier.h.
    129          * We are safe to turn these on.
    130          */
    131         control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
     109        /* Turn off tex remap */
     110        control_reg &= ~CP15_R1_TRE_BIT;
     111        /* Turn off accessed flag */
     112        control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT);
     113        /* Enable caching */
     114        control_reg |= CP15_R1_CACHE_ENABLE_BIT;
    132115       
    133116        asm volatile (
    … …  
    139122
    140123/** Retrieves processor identification and stores it to #CPU.arch */
    141 void cpu_identify(void)
     124void cpu_identify(void) 
    142125{
    143126        arch_cpu_identify(&CPU->arch);
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