Changeset 4b28c70 in mainline
- Timestamp:
- 2013-01-19T22:59:00Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3fa509b
- Parents:
- c3213bb
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/cpu/cpu.c
rc3213bb r4b28c70 225 225 unsigned dcache_levels(void) 226 226 { 227 unsigned levels = 0; 228 #ifdef PROCESSOR_ARCH_armv7_a 227 229 const uint32_t val = CLIDR_read(); 228 unsigned levels = 0;229 230 for (unsigned i = 1; i <= 7; ++i) { 230 231 const unsigned ctype = CLIDR_CACHE(i, val); … … 238 239 } 239 240 } 241 #endif 240 242 return levels; 241 243 }
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