Changes in / [0743493a:4ce90544] in mainline

Location:

kernel/arch/ia64

Files:

• include/register.h (modified) (1 diff)
• src/ivt.S (modified) (2 diffs)

kernel/arch/ia64/include/register.h

@@ -60 +60 @@
 #define PSR_CPL_SHIFT         32
 #define PSR_CPL_MASK_SHIFTED  3
+
+#define PSR_RI_SHIFT    41
+#define PSR_RI_LEN      2
 
 #define PFM_MASK  (~0x3fffffffff)

kernel/arch/ia64/src/ivt.S

@@ -50 +50 @@
 #define R_KSTACK_BSP    r22     /* keep in sync with before_thread_runs_arch() */
 #define R_KSTACK        r23     /* keep in sync with before_thread_runs_arch() */
+
+/* Speculation vector handler */
+.macro SPECULATION_VECTOR_HANDLER offs
+    .org ivt + \offs
+
+    /* 1. Save predicates, IIM, IIP, IPSR and ISR CR's in bank 0 registers. */
+        mov r16 = pr
+        mov r17 = cr.iim
+        mov r18 = cr.iip
+        mov r19 = cr.ipsr
+        mov r20 = cr.isr ;;
+        
+    /* 2. Move IIP to IIPA. */
+        mov cr.iipa = r18
+        
+    /* 3. Sign extend IIM[20:0], shift left by 4 and add to IIP. */
+        shl r17 = r17, 43 ;;    /* shift bit 20 to bit 63 */
+        shr r17 = r17, 39 ;;    /* signed shift right to bit 24 */
+        add r18 = r18, r17 ;;
+        mov cr.iip = r18
+        
+    /* 4. Set IPSR.ri to 0. */
+        dep r19 = 0, r19, PSR_RI_SHIFT, PSR_RI_LEN ;;
+        mov cr.ipsr = r19
+        
+    /* 5. Check whether IPSR.tb or IPSR.ss is set. */
+
+        /* TODO:
+         * Implement this when Taken Branch and Single Step traps can occur.
+         */
+    
+    /* 6. Restore predicates and return from interruption. */
+        mov pr = r16 ;;
+        rfi
+.endm
 
 /** Heavyweight interrupt handler
@@ -541 +576 @@
         HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
         HEAVYWEIGHT_HANDLER 0x5600
-        HEAVYWEIGHT_HANDLER 0x5700
+        SPECULATION_VECTOR_HANDLER 0x5700
         HEAVYWEIGHT_HANDLER 0x5800
         HEAVYWEIGHT_HANDLER 0x5900