Changeset 4fb6bf36 in mainline

Timestamp:

2008-01-11T17:49:35Z (17 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0ee4322

Parents:

eb27ce5a

Message:

move cpuid tests from amd64.c to boot.S

Location:

kernel/arch/amd64

Files:

• include/cpuid.h (modified) (1 diff)
• src/amd64.c (modified) (2 diffs)
• src/boot/boot.S (modified) (5 diffs)

kernel/arch/amd64/include/cpuid.h

@@ -38 +38 @@
 #define AMD_CPUID_EXTENDED   0x80000001
 #define AMD_EXT_NOEXECUTE    20
+#define AMD_EXT_LONG_MODE    29
 
-#define INTEL_CPUID_STANDARD 0x1
+#define INTEL_CPUID_STANDARD 0x00000001
+#define INTEL_CPUID_EXTENDED 0x80000000
 #define INTEL_SSE2           26
 #define INTEL_FXSAVE         24

kernel/arch/amd64/src/amd64.c

@@ -104 +104 @@
 void arch_pre_mm_init(void)
 {
-        cpu_info_t cpuid_s;
-
-        cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
-        if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
-                panic("Processor does not support No-execute pages.\n");
-
-        cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
-        if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
-                panic("Processor does not support FXSAVE/FXRESTORE.\n");
-        
-        if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
-                panic("Processor does not support SSE2 instructions.\n");
-
-        /* Enable No-execute pages */
+        /* Enable no-execute pages */
         set_efer_flag(AMD_NXE_FLAG);
         /* Enable FPU */
@@ -124 +111 @@
         /* Initialize segmentation */
         pm_init();
-
-        /* Disable I/O on nonprivileged levels
-         * clear the NT(nested-thread) flag 
+        
+        /* Disable I/O on nonprivileged levels
+         * clear the NT (nested-thread) flag 
          */
         clean_IOPL_NT_flags();

kernel/arch/amd64/src/boot/boot.S

@@ -1 @@
-#
+
 # Copyright (c) 2005 Ondrej Palkovsky
 # Copyright (c) 2006 Martin Decky
@@ -76 +76 @@
         # the Default operand size must not be 1 when entering long mode
         
-        movl $0x80000000, %eax  
+        movl $(INTEL_CPUID_EXTENDED), %eax  
         cpuid
-        cmp $0x80000000, %eax                                           # any function > 80000000h?
-        jbe long_mode_unsupported
-        movl $(AMD_CPUID_EXTENDED), %eax                        # Extended function code 80000001
+        cmp $(INTEL_CPUID_EXTENDED), %eax
+        ja extended_cpuid_supported
+                
+                movl $extended_cpuid_msg, %esi
+                jmp error_halt
+        
+        extended_cpuid_supported:
+        
+        movl $(AMD_CPUID_EXTENDED), %eax
         cpuid
-        bt $29, %edx                                                            # Test if long mode is supported.
+        bt $(AMD_EXT_LONG_MODE), %edx
         jc long_mode_supported
-
-        long_mode_unsupported:
+                
                 movl $long_mode_msg, %esi
                 jmp error_halt
-        
+
         long_mode_supported:
+        
+        bt $(AMD_EXT_NOEXECUTE), %edx
+        jc noexecute_supported
+        
+                movl $noexecute_msg, %esi
+                jmp error_halt
+        
+        noexecute_supported:
+        
+        movl $(INTEL_CPUID_STANDARD), %eax
+        cpuid
+        bt $(INTEL_FXSAVE), %edx
+        jc fx_supported
+        
+                movl $fx_msg, %esi
+                jmp error_halt
+        
+        fx_supported:
+        
+        bt $(INTEL_SSE2), %edx
+        jc sse2_supported
+        
+                movl $sse2_msg, %esi
+                jmp error_halt
+        
+        sse2_supported:
         
 #ifdef CONFIG_FB
@@ -112 +143 @@
 #endif  
         
-        # Enable 64-bit page transaltion entries - CR4.PAE = 1.
+        # Enable 64-bit page translation entries - CR4.PAE = 1.
         # Paging is not enabled until after long mode is enabled
         
@@ -128 +159 @@
         movl $EFER_MSR_NUM, %ecx        # EFER MSR number
         rdmsr                                           # Read EFER
-        btsl $AMD_LME_FLAG, %eax        # Set LME=1
+        btsl $AMD_LME_FLAG, %eax        # Set LME = 1
         wrmsr                                           # Write EFER
         
-        # Enable paging to activate long mode (set CR0.PG=1)
+        # Enable paging to activate long mode (set CR0.PG = 1)
         
         movl %cr0, %eax
@@ -636 +667 @@
         .long 0
 
+extended_cpuid_msg:
+        .asciz "Extended CPUID not supported. System halted."
 long_mode_msg:
         .asciz "64 bit long mode not supported. System halted."
+noexecute_msg:
+        .asciz "No-execute pages not supported. System halted."
+fx_msg:
+        .asciz "FXSAVE/FXRESTORE instructions not supported. System halted."
+sse2_msg:
+        .asciz "SSE2 instructions not supported. System halted."