Changes in kernel/arch/abs32le/include/atomic.h [b03a666:50fda24] in mainline

File:

• kernel/arch/abs32le/include/atomic.h (modified) (5 diffs)

kernel/arch/abs32le/include/atomic.h

@@ -54 +54 @@
 }
 
-static inline atomic_count_t atomic_postinc(atomic_t *val)
+static inline long atomic_postinc(atomic_t *val)
 {
         /* On real hardware both the storing of the previous
@@ -60 +60 @@
            atomic action. */
         
-        atomic_count_t prev = val->count;
+        long prev = val->count;
         
         val->count++;
@@ -66 +66 @@
 }
 
-static inline atomic_count_t atomic_postdec(atomic_t *val)
+static inline long atomic_postdec(atomic_t *val)
 {
         /* On real hardware both the storing of the previous
@@ -72 +72 @@
            atomic action. */
         
-        atomic_count_t prev = val->count;
+        long prev = val->count;
         
         val->count--;
@@ -81 +81 @@
 #define atomic_predec(val)  (atomic_postdec(val) - 1)
 
-static inline atomic_count_t test_and_set(atomic_t *val)
-{
-        atomic_count_t prev = val->count;
-        val->count = 1;
-        return prev;
+static inline uint32_t test_and_set(atomic_t *val) {
+        uint32_t v;
+        
+        asm volatile (
+                "movl $1, %[v]\n"
+                "xchgl %[v], %[count]\n"
+                : [v] "=r" (v), [count] "+m" (val->count)
+        );
+        
+        return v;
 }
 
+/** ia32 specific fast spinlock */
 static inline void atomic_lock_arch(atomic_t *val)
 {
-        do {
-                while (val->count);
-        } while (test_and_set(val));
+        uint32_t tmp;
+        
+        preemption_disable();
+        asm volatile (
+                "0:\n"
+                "pause\n"        /* Pentium 4's HT love this instruction */
+                "mov %[count], %[tmp]\n"
+                "testl %[tmp], %[tmp]\n"
+                "jnz 0b\n"       /* lightweight looping on locked spinlock */
+                
+                "incl %[tmp]\n"  /* now use the atomic operation */
+                "xchgl %[count], %[tmp]\n"
+                "testl %[tmp], %[tmp]\n"
+                "jnz 0b\n"
+                : [count] "+m" (val->count), [tmp] "=&r" (tmp)
+        );
+        /*
+         * Prevent critical section code from bleeding out this way up.
+         */
+        CS_ENTER_BARRIER();
 }