Changeset 53f9821 in mainline for arch/amd64/include/atomic.h

Timestamp:

2006-03-20T20:32:17Z (19 years ago)

Author:

Ondrej Palkovsky <ondrap@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

018d957e

Parents:

9d3e185

Message:

Cleanup of spinlocks, now compiles both ia32 and amd64 with
and without DEBUG_SPINLOCKS. Made spinlocks inline.
Moved syscall_handler to generic (it was identical for ia32,amd64 & mips32).
Made slightly faster syscall for ia32.
Made better interrupt routines for ia32.
Allow not saving non-scratch registers during interrupt on ia32,amd64,mips32.
Aligned interrupt handlers on ia32,amd64, this should prevent problems
with different instruction lengths.

File:

• arch/amd64/include/atomic.h (modified) (2 diffs)

arch/amd64/include/atomic.h

@@ -31 +31 @@
 
 #include <arch/types.h>
+#include <arch/barrier.h>
+#include <preemption.h>
 
 typedef struct { volatile __u64 count; } atomic_t;
@@ -102 +104 @@
 
 
-extern void spinlock_arch(volatile int *val);
+/** AMD64 specific fast spinlock */
+static inline void atomic_lock_arch(atomic_t *val)
+{
+        __u64 tmp;
+
+        preemption_disable();
+        __asm__ volatile (
+                "0:;"
+#ifdef CONFIG_HT
+                "pause;" /* Pentium 4's HT love this instruction */
+#endif
+                "mov %0, %1;"
+                "testq %1, %1;"
+                "jnz 0b;"       /* Leightweight looping on locked spinlock */
+                
+                "incq %1;"      /* now use the atomic operation */
+                "xchgq %0, %1;"
+                "testq %1, %1;"
+                "jnz 0b;"
+                : "=m"(val->count),"=r"(tmp)
+                );
+        /*
+         * Prevent critical section code from bleeding out this way up.
+         */
+        CS_ENTER_BARRIER();
+}
 
 #endif