Changes in / [42bde6a:54a0070] in mainline
- Files:
-
- 26 added
- 21 deleted
- 12 edited
Legend:
- Unmodified
- Added
- Removed
-
defaults/amd64/Makefile.config
r42bde6a r54a0070 54 54 55 55 # Default framebuffer mode 56 CONFIG_BFB_MODE = 800x60056 CONFIG_BFB_MODE = 1024x768 57 57 58 58 # Default framebuffer depth -
defaults/ia32/Makefile.config
r42bde6a r54a0070 60 60 61 61 # Default framebuffer mode 62 CONFIG_BFB_MODE = 800x60062 CONFIG_BFB_MODE = 1024x768 63 63 64 64 # Default framebuffer depth -
kernel/arch/arm32/Makefile.inc
r42bde6a r54a0070 33 33 ATSIGN = % 34 34 35 GCC_CFLAGS += -march=armv4 35 GCC_CFLAGS += -march=armv4 -fno-omit-frame-pointer -mapcs-frame 36 36 37 37 BITS = 32 -
kernel/arch/arm32/include/istate.h
r42bde6a r54a0070 49 49 /** Struct representing CPU state saved when an exception occurs. */ 50 50 typedef struct istate { 51 uint32_t dummy; 51 52 uint32_t spsr; 52 53 uint32_t sp; -
kernel/arch/arm32/src/exc_handler.S
r42bde6a r54a0070 130 130 stmfd r13!, {r2} 131 131 2: 132 sub sp, sp, #4 132 133 .endm 133 134 134 135 .macro LOAD_REGS_FROM_STACK 136 add sp, sp, #4 135 137 ldmfd r13!, {r0} 136 138 msr spsr, r0 -
kernel/arch/arm32/src/mm/page_fault.c
r42bde6a r54a0070 77 77 } 78 78 79 /** Decides whether the instruction is load/store or not.80 *81 * @param instr Instruction82 *83 * @return true when instruction is load/store, false otherwise84 *85 */86 static inline bool is_load_store_instruction(instruction_t instr)87 {88 /* load store immediate offset */89 if (instr.type == 0x2)90 return true;91 92 /* load store register offset */93 if ((instr.type == 0x3) && (instr.bit4 == 0))94 return true;95 96 /* load store multiple */97 if (instr.type == 0x4)98 return true;99 100 /* oprocessor load/store */101 if (instr.type == 0x6)102 return true;103 104 return false;105 }106 107 /** Decides whether the instruction is swap or not.108 *109 * @param instr Instruction110 *111 * @return true when instruction is swap, false otherwise112 */113 static inline bool is_swap_instruction(instruction_t instr)114 {115 /* swap, swapb instruction */116 if ((instr.type == 0x0) &&117 ((instr.opcode == 0x8) || (instr.opcode == 0xa)) &&118 (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1))119 return true;120 121 return false;122 }123 124 79 /** Decides whether read or write into memory is requested. 125 80 * … … 128 83 * 129 84 * @return Type of access into memory, PF_ACCESS_EXEC if no memory access is 130 * 85 * requested. 131 86 */ 132 87 static pf_access_t get_memory_access_type(uint32_t instr_addr, … … 146 101 } 147 102 148 /* load store instructions */ 149 if (is_load_store_instruction(instr)) { 150 if (instr.access == 1) { 151 return PF_ACCESS_READ; 152 } else { 153 return PF_ACCESS_WRITE; 103 /* See ARM Architecture reference manual ARMv7-A and ARMV7-R edition 104 * A5.3 (PDF p. 206) */ 105 static const struct { 106 uint32_t mask; 107 uint32_t value; 108 pf_access_t access; 109 } ls_inst[] = { 110 /* Store word/byte */ 111 { 0x0e100000, 0x04000000, PF_ACCESS_WRITE }, /*STR(B) imm*/ 112 { 0x0e100010, 0x06000000, PF_ACCESS_WRITE }, /*STR(B) reg*/ 113 /* Load word/byte */ 114 { 0x0e100000, 0x04100000, PF_ACCESS_READ }, /*LDR(B) imm*/ 115 { 0x0e100010, 0x06100000, PF_ACCESS_READ }, /*LDR(B) reg*/ 116 /* Store half-word/dual A5.2.8 */ 117 { 0x0e1000b0, 0x000000b0, PF_ACCESS_WRITE }, /*STRH imm reg*/ 118 /* Load half-word/dual A5.2.8 */ 119 { 0x0e0000f0, 0x000000d0, PF_ACCESS_READ }, /*LDRH imm reg*/ 120 { 0x0e1000b0, 0x001000b0, PF_ACCESS_READ }, /*LDRH imm reg*/ 121 /* Block data transfer, Store */ 122 { 0x0e100000, 0x08000000, PF_ACCESS_WRITE }, /* STM variants */ 123 { 0x0e100000, 0x08100000, PF_ACCESS_READ }, /* LDM variants */ 124 /* Swap */ 125 { 0x0fb00000, 0x01000000, PF_ACCESS_WRITE }, 126 }; 127 const uint32_t inst = *(uint32_t*)instr_addr; 128 for (unsigned i = 0; i < sizeof(ls_inst) / sizeof(ls_inst[0]); ++i) { 129 if ((inst & ls_inst[i].mask) == ls_inst[i].value) { 130 return ls_inst[i].access; 154 131 } 155 }156 157 /* swap, swpb instruction */158 if (is_swap_instruction(instr)) {159 return PF_ACCESS_WRITE;160 132 } 161 133 162 134 panic("page_fault - instruction doesn't access memory " 163 135 "(instr_code: %#0" PRIx32 ", badvaddr:%p).", 164 instr_union.pc, (void *) badvaddr); 165 166 return PF_ACCESS_EXEC; 136 inst, (void *) badvaddr); 167 137 } 168 138 -
uspace/app/tester/Makefile
r42bde6a r54a0070 29 29 30 30 USPACE_PREFIX = ../.. 31 LIBS = $(LIBEXT2_PREFIX)/libext2.a $(LIBBLOCK_PREFIX)/libblock.a 32 EXTRA_CFLAGS = -I$(LIBBLOCK_PREFIX) -I$(LIBEXT2_PREFIX) 31 LIBS = $(LIBEXT2_PREFIX)/libext2.a $(LIBBLOCK_PREFIX)/libblock.a $(LIBSOFTFLOAT_PREFIX)/libsoftfloat.a 32 EXTRA_CFLAGS = -I$(LIBBLOCK_PREFIX) -I$(LIBEXT2_PREFIX) -I$(LIBSOFTFLOAT_PREFIX) 33 33 BINARY = tester 34 34 … … 50 50 fault/fault2.c \ 51 51 fault/fault3.c \ 52 float/float1.c \ 53 float/softfloat1.c \ 52 54 vfs/vfs1.c \ 53 55 ipc/ping_pong.c \ … … 61 63 hw/misc/virtchar1.c \ 62 64 hw/serial/serial1.c \ 63 libext2/libext2_1.c65 ext2/ext2_1.c 64 66 65 67 include $(USPACE_PREFIX)/Makefile.common -
uspace/app/tester/tester.c
r42bde6a r54a0070 61 61 #include "fault/fault2.def" 62 62 #include "fault/fault3.def" 63 #include "float/float1.def" 64 #include "float/softfloat1.def" 63 65 #include "vfs/vfs1.def" 64 66 #include "ipc/ping_pong.def" … … 71 73 #include "hw/serial/serial1.def" 72 74 #include "hw/misc/virtchar1.def" 73 #include " libext2/libext2_1.def"75 #include "ext2/ext2_1.def" 74 76 {NULL, NULL, NULL, false} 75 77 }; -
uspace/app/tester/tester.h
r42bde6a r54a0070 93 93 extern const char *test_fault2(void); 94 94 extern const char *test_fault3(void); 95 extern const char *test_float1(void); 96 extern const char *test_softfloat1(void); 95 97 extern const char *test_vfs1(void); 96 98 extern const char *test_ping_pong(void); … … 103 105 extern const char *test_serial1(void); 104 106 extern const char *test_virtchar1(void); 105 extern const char *test_ libext2_1(void);107 extern const char *test_ext2_1(void); 106 108 extern const char *test_devman1(void); 107 109 extern const char *test_devman2(void); -
uspace/lib/c/arch/arm32/Makefile.common
r42bde6a r54a0070 28 28 # 29 29 30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4 30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -march=armv4 -mapcs-frame 31 31 32 32 ENDIANESS = LE -
uspace/lib/fs/libfs.c
r42bde6a r54a0070 631 631 async_answer_0(rid, rc); 632 632 } else { 633 aoff64_t size = ops->size_get(fn); 634 async_answer_5(rid, fs_handle, 635 service_id, 636 ops->index_get(fn), 637 LOWER32(size), 638 UPPER32(size), 639 ops->lnkcnt_get(fn)); 640 (void) ops->node_put(fn); 633 (void) ops->node_put(cur); 634 cur = fn; 635 goto out_with_answer; 641 636 } 642 637 } else … … 715 710 async_answer_0(rid, rc); 716 711 } else { 717 aoff64_t size = ops->size_get(fn); 718 async_answer_5(rid, fs_handle, 719 service_id, 720 ops->index_get(fn), 721 LOWER32(size), 722 UPPER32(size), 723 ops->lnkcnt_get(fn)); 724 (void) ops->node_put(fn); 712 (void) ops->node_put(cur); 713 cur = fn; 714 goto out_with_answer; 725 715 } 726 716 } else -
uspace/lib/softfloat/Makefile
r42bde6a r54a0070 29 29 30 30 USPACE_PREFIX = ../.. 31 EXTRA_CFLAGS = -Iinclude32 31 LIBRARY = libsoftfloat 33 32 34 33 SOURCES = \ 35 generic/add.c \36 generic/common.c \37 generic/comparison.c \38 generic/conversion.c \39 generic/div.c \40 generic/mul.c \41 generic/other.c \42 generic/softfloat.c \43 generic/sub.c34 softfloat.c \ 35 common.c \ 36 add.c \ 37 sub.c \ 38 div.c \ 39 mul.c \ 40 comparison.c \ 41 conversion.c \ 42 other.c 44 43 45 44 include $(USPACE_PREFIX)/Makefile.common
Note:
See TracChangeset
for help on using the changeset viewer.