Changes in uspace/lib/c/arch/arm32/src/atomic.c [133461c:56210a7] in mainline

File:

• uspace/lib/c/arch/arm32/src/atomic.c (modified) (2 diffs)

uspace/lib/c/arch/arm32/src/atomic.c

@@ -86 +86 @@
 }
 
+unsigned char __atomic_exchange_1(volatile void *mem0, unsigned char val,
+    int model)
+{
+        volatile unsigned char *mem = mem0;
+
+        (void) model;
+
+        unsigned ret;
+
+        /*
+         * The following instructions between labels 1 and 2 constitute a
+         * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
+         * the kernel will restart it.
+         */
+        asm volatile (
+            "1:\n"
+            "   adr %[ret], 1b\n"
+            "   str %[ret], %[rp0]\n"
+            "   adr %[ret], 2f\n"
+            "   str %[ret], %[rp1]\n"
+            "   ldrb %[ret], %[addr]\n"
+            "   strb %[imm], %[addr]\n"
+            "2:\n"
+            : [ret] "=&r" (ret),
+              [rp0] "=m" (ras_page[0]),
+              [rp1] "=m" (ras_page[1]),
+              [addr] "+m" (*mem)
+            : [imm] "r" (val)
+        );
+
+        ras_page[0] = 0;
+        ras_page[1] = 0xffffffff;
+
+        return ret;
+}
+
+unsigned short __atomic_exchange_2(volatile void *mem0, unsigned short val,
+    int model)
+{
+        volatile unsigned short *mem = mem0;
+
+        (void) model;
+
+        unsigned ret;
+
+        /*
+         * The following instructions between labels 1 and 2 constitute a
+         * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
+         * the kernel will restart it.
+         */
+        asm volatile (
+            "1:\n"
+            "   adr %[ret], 1b\n"
+            "   str %[ret], %[rp0]\n"
+            "   adr %[ret], 2f\n"
+            "   str %[ret], %[rp1]\n"
+            "   ldrh %[ret], %[addr]\n"
+            "   strh %[imm], %[addr]\n"
+            "2:\n"
+            : [ret] "=&r" (ret),
+              [rp0] "=m" (ras_page[0]),
+              [rp1] "=m" (ras_page[1]),
+              [addr] "+m" (*mem)
+            : [imm] "r" (val)
+        );
+
+        ras_page[0] = 0;
+        ras_page[1] = 0xffffffff;
+
+        return ret;
+}
+
+unsigned __atomic_exchange_4(volatile void *mem0, unsigned val, int model)
+{
+        volatile unsigned *mem = mem0;
+
+        (void) model;
+
+        unsigned ret;
+
+        /*
+         * The following instructions between labels 1 and 2 constitute a
+         * Restartable Atomic Seqeunce. Should the sequence be non-atomic,
+         * the kernel will restart it.
+         */
+        asm volatile (
+            "1:\n"
+            "   adr %[ret], 1b\n"
+            "   str %[ret], %[rp0]\n"
+            "   adr %[ret], 2f\n"
+            "   str %[ret], %[rp1]\n"
+            "   ldr %[ret], %[addr]\n"
+            "   str %[imm], %[addr]\n"
+            "2:\n"
+            : [ret] "=&r" (ret),
+              [rp0] "=m" (ras_page[0]),
+              [rp1] "=m" (ras_page[1]),
+              [addr] "+m" (*mem)
+            : [imm] "r" (val)
+        );
+
+        ras_page[0] = 0;
+        ras_page[1] = 0xffffffff;
+
+        return ret;
+}
+
 unsigned short __atomic_fetch_add_2(volatile void *mem0, unsigned short val,
     int model)
@@ -164 +271 @@
 }
 
+bool __atomic_test_and_set(volatile void *ptr, int memorder)
+{
+        volatile unsigned char *b = ptr;
+
+        unsigned char orig = __atomic_exchange_n(b, (unsigned char) true, memorder);
+        return orig != 0;
+}
+
 void __sync_synchronize(void)
 {