Changes in uspace/lib/c/arch/arm32/src/atomic.c [ae787807:56210a7] in mainline
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uspace/lib/c/arch/arm32/src/atomic.c
rae787807 r56210a7 38 38 volatile unsigned *ras_page; 39 39 40 unsigned long long __atomic_load_8(const volatile void *mem0, int model)41 {42 const volatile unsigned long long *mem = mem0;43 44 (void) model;45 46 unsigned long long ret;47 48 /*49 * The following instructions between labels 1 and 2 constitute a50 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,51 * the kernel will restart it.52 */53 asm volatile (54 "1:\n"55 " adr %[ret], 1b\n"56 " str %[ret], %[rp0]\n"57 " adr %[ret], 2f\n"58 " str %[ret], %[rp1]\n"59 60 " ldrd %[ret], %[addr]\n"61 "2:\n"62 : [ret] "=&r" (ret),63 [rp0] "=m" (ras_page[0]),64 [rp1] "=m" (ras_page[1])65 : [addr] "m" (*mem)66 );67 68 ras_page[0] = 0;69 ras_page[1] = 0xffffffff;70 71 return ret;72 }73 74 void __atomic_store_8(volatile void *mem0, unsigned long long val, int model)75 {76 volatile unsigned long long *mem = mem0;77 78 (void) model;79 80 /* scratch register */81 unsigned tmp;82 83 /*84 * The following instructions between labels 1 and 2 constitute a85 * Restartable Atomic Seqeunce. Should the sequence be non-atomic,86 * the kernel will restart it.87 */88 asm volatile (89 "1:\n"90 " adr %[tmp], 1b\n"91 " str %[tmp], %[rp0]\n"92 " adr %[tmp], 2f\n"93 " str %[tmp], %[rp1]\n"94 95 " strd %[imm], %[addr]\n"96 "2:\n"97 : [tmp] "=&r" (tmp),98 [rp0] "=m" (ras_page[0]),99 [rp1] "=m" (ras_page[1]),100 [addr] "=m" (*mem)101 : [imm] "r" (val)102 );103 104 ras_page[0] = 0;105 ras_page[1] = 0xffffffff;106 }107 108 40 bool __atomic_compare_exchange_4(volatile void *mem0, void *expected0, 109 41 unsigned desired, bool weak, int success, int failure)
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