Changeset 567807b1 in mainline for arch/ia64/src/mm/tlb.c

Timestamp:

2006-05-24T17:03:29Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

8d6bc2d5

Parents:

82da5f5

Message:

Modify the hierarchy of page fault handlers to pass access mode that caused the fault.
Architectures are required to pass either PF_ACCESS_READ, PF_ACCESS_WRITE or PF_ACCESS_EXEC
to as_page_fault(), depending on the cause of the fault.

File:

• arch/ia64/src/mm/tlb.c (modified) (5 diffs)

arch/ia64/src/mm/tlb.c

@@ -430 +430 @@
 {
         region_register rr;
+        rid_t rid;
         __address va;
         pte_t *t;
         
         va = istate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
+
         page_table_lock(AS, true);
         t = page_mapping_find(AS, va);
@@ -448 +452 @@
                  */
                 page_table_unlock(AS, true);
-                if (as_page_fault(va, istate) == AS_PF_FAULT) {
-                        panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, istate->cr_ifa, rr.map.rid, istate->cr_iip);
+                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+                        panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
                 }
         }
@@ -494 +498 @@
                  */
                 page_table_unlock(AS, true);
-                if (as_page_fault(va, istate) == AS_PF_FAULT) {
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
                         panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
                 }
@@ -519 +523 @@
 void data_dirty_bit_fault(__u64 vector, istate_t *istate)
 {
+        region_register rr;
+        rid_t rid;
+        __address va;
         pte_t *t;
+        
+        va = istate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
 
         page_table_lock(AS, true);
-        t = page_mapping_find(AS, istate->cr_ifa);
+        t = page_mapping_find(AS, va);
+        ASSERT(t && t->p);
+        if (t && t->p && t->w) {
+                /*
+                 * Update the Dirty bit in page tables and reinsert
+                 * the mapping into DTC.
+                 */
+                t->d = true;
+                dtc_pte_copy(t);
+        } else {
+                if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+                        panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+                        t->d = true;
+                        dtc_pte_copy(t);
+                }
+        }
+        page_table_unlock(AS, true);
+}
+
+/** Instruction access bit fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void instruction_access_bit_fault(__u64 vector, istate_t *istate)
+{
+        region_register rr;
+        rid_t rid;
+        __address va;
+        pte_t *t;       
+
+        va = istate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
+
+        page_table_lock(AS, true);
+        t = page_mapping_find(AS, va);
+        ASSERT(t && t->p);
+        if (t && t->p && t->x) {
+                /*
+                 * Update the Accessed bit in page tables and reinsert
+                 * the mapping into ITC.
+                 */
+                t->a = true;
+                itc_pte_copy(t);
+        } else {
+                if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+                        panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+                        t->a = true;
+                        itc_pte_copy(t);
+                }
+        }
+        page_table_unlock(AS, true);
+}
+
+/** Data access bit fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void data_access_bit_fault(__u64 vector, istate_t *istate)
+{
+        region_register rr;
+        rid_t rid;
+        __address va;
+        pte_t *t;
+
+        va = istate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
+
+        page_table_lock(AS, true);
+        t = page_mapping_find(AS, va);
         ASSERT(t && t->p);
         if (t && t->p) {
                 /*
-                 * Update the Dirty bit in page tables and reinsert
+                 * Update the Accessed bit in page tables and reinsert
                  * the mapping into DTC.
                  */
-                t->d = true;
+                t->a = true;
                 dtc_pte_copy(t);
+        } else {
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+                        t->a = true;
+                        itc_pte_copy(t);
+                }
         }
         page_table_unlock(AS, true);
 }
 
-/** Instruction access bit fault handler.
+/** Page not present fault handler.
  *
  * @param vector Interruption vector.
  * @param istate Structure with saved interruption state.
  */
-void instruction_access_bit_fault(__u64 vector, istate_t *istate)
-{
-        pte_t *t;
-
-        page_table_lock(AS, true);
-        t = page_mapping_find(AS, istate->cr_ifa);
-        ASSERT(t && t->p);
-        if (t && t->p) {
-                /*
-                 * Update the Accessed bit in page tables and reinsert
-                 * the mapping into ITC.
-                 */
-                t->a = true;
-                itc_pte_copy(t);
-        }
-        page_table_unlock(AS, true);
-}
-
-/** Data access bit fault handler.
- *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
- */
-void data_access_bit_fault(__u64 vector, istate_t *istate)
-{
-        pte_t *t;
-
-        page_table_lock(AS, true);
-        t = page_mapping_find(AS, istate->cr_ifa);
-        ASSERT(t && t->p);
-        if (t && t->p) {
-                /*
-                 * Update the Accessed bit in page tables and reinsert
-                 * the mapping into DTC.
-                 */
-                t->a = true;
-                dtc_pte_copy(t);
-        }
-        page_table_unlock(AS, true);
-}
-
-/** Page not present fault handler.
- *
- * @param vector Interruption vector.
- * @param istate Structure with saved interruption state.
- */
 void page_not_present(__u64 vector, istate_t *istate)
 {
         region_register rr;
+        rid_t rid;
         __address va;
         pte_t *t;
         
         va = istate->cr_ifa;    /* faulting address */
+        rr.word = rr_read(VA2VRN(va));
+        rid = rr.map.rid;
+
         page_table_lock(AS, true);
         t = page_mapping_find(AS, va);
@@ -609 +656 @@
         } else {
                 page_table_unlock(AS, true);
-                if (as_page_fault(va, istate) == AS_PF_FAULT) {
-                        panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rr.map.rid);
-                }
-        }
-}
+                if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+                        panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rid);
+                }
+        }
+}