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  • kernel/arch/mips32/include/cp0.h

    r84f0a79 r598f90e  
    7070  { \
    7171      uint32_t retval; \
    72       asm volatile ("mfc0 %0, $" #reg : "=r"(retval)); \
     72      asm("mfc0 %0, $" #reg : "=r"(retval)); \
    7373      return retval; \
    7474  }
     
    7676#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(uint32_t val) \
    7777 { \
    78     asm volatile ("mtc0 %0, $" #reg : : "r"(val) ); \
     78    asm("mtc0 %0, $" #reg : : "r"(val) ); \
    7979 }
    8080
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