Changes in kernel/arch/mips32/src/mm/tlb.c [346b12a2:59fb782] in mainline
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kernel/arch/mips32/src/mm/tlb.c
r346b12a2 r59fb782 43 43 #include <synch/mutex.h> 44 44 #include <print.h> 45 #include <log.h>46 45 #include <debug.h> 47 46 #include <align.h> … … 49 48 #include <symtab.h> 50 49 51 #define PFN_SHIFT 12 52 #define VPN_SHIFT 12 53 54 #define ADDR2HI_VPN(a) ((a) >> VPN_SHIFT) 55 #define ADDR2HI_VPN2(a) (ADDR2HI_VPN((a)) >> 1) 56 57 #define HI_VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) 58 #define HI_VPN22ADDR(vpn2) (HI_VPN2ADDR(vpn2) << 1) 59 60 #define LO_PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) 61 62 #define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) 50 #define PFN_SHIFT 12 51 #define VPN_SHIFT 12 52 #define ADDR2VPN(a) ((a) >> VPN_SHIFT) 53 #define ADDR2VPN2(a) (ADDR2VPN((a)) >> 1) 54 #define VPN2ADDR(vpn) ((vpn) << VPN_SHIFT) 55 #define VPN22ADDR(vpn2) (VPN2ADDR(vpn2) << 1) 56 #define PFN2ADDR(pfn) ((pfn) << PFN_SHIFT) 57 58 #define BANK_SELECT_BIT(a) (((a) >> PAGE_WIDTH) & 1) 59 63 60 64 61 /** Initialize TLB. … … 97 94 entry_lo_t lo; 98 95 uintptr_t badvaddr; 99 pte_t pte;96 pte_t *pte; 100 97 101 98 badvaddr = cp0_badvaddr_read(); 102 99 103 bool found = page_mapping_find(AS, badvaddr, true, &pte);104 if ( found && pte.p) {100 pte = page_mapping_find(AS, badvaddr, true); 101 if (pte && pte->p) { 105 102 /* 106 103 * Record access to PTE. 107 104 */ 108 pte.a = 1; 109 110 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 111 pte.cacheable, pte.pfn); 112 113 page_mapping_update(AS, badvaddr, true, &pte); 105 pte->a = 1; 106 107 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 108 pte->cacheable, pte->pfn); 114 109 115 110 /* … … 140 135 tlb_index_t index; 141 136 uintptr_t badvaddr; 142 pte_t pte;137 pte_t *pte; 143 138 144 139 /* … … 164 159 badvaddr = cp0_badvaddr_read(); 165 160 166 bool found = page_mapping_find(AS, badvaddr, true, &pte);167 if ( found && pte.p) {161 pte = page_mapping_find(AS, badvaddr, true); 162 if (pte && pte->p) { 168 163 /* 169 164 * Read the faulting TLB entry. … … 174 169 * Record access to PTE. 175 170 */ 176 pte.a = 1; 177 178 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.d, 179 pte.cacheable, pte.pfn); 180 181 page_mapping_update(AS, badvaddr, true, &pte); 171 pte->a = 1; 172 173 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, 174 pte->cacheable, pte->pfn); 182 175 183 176 /* … … 204 197 tlb_index_t index; 205 198 uintptr_t badvaddr; 206 pte_t pte;199 pte_t *pte; 207 200 208 201 badvaddr = cp0_badvaddr_read(); … … 222 215 */ 223 216 if (index.p) { 224 log(LF_ARCH, LVL_WARN,"%s: TLBP failed in exception handler (badvaddr=%#"217 printf("%s: TLBP failed in exception handler (badvaddr=%#" 225 218 PRIxn ", ASID=%d).\n", __func__, badvaddr, 226 219 AS ? AS->asid : -1); … … 228 221 } 229 222 230 bool found = page_mapping_find(AS, badvaddr, true, &pte);231 if ( found && pte.p && pte.w) {223 pte = page_mapping_find(AS, badvaddr, true); 224 if (pte && pte->p && pte->w) { 232 225 /* 233 226 * Read the faulting TLB entry. … … 238 231 * Record access and write to PTE. 239 232 */ 240 pte.a = 1; 241 pte.d = 1; 242 243 tlb_prepare_entry_lo(&lo, pte.g, pte.p, pte.w, 244 pte.cacheable, pte.pfn); 245 246 page_mapping_update(AS, badvaddr, true, &pte); 233 pte->a = 1; 234 pte->d = 1; 235 236 tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, 237 pte->cacheable, pte->pfn); 247 238 248 239 /* … … 275 266 { 276 267 hi->value = 0; 277 hi->vpn2 = ADDR2 HI_VPN2(ALIGN_DOWN(addr, PAGE_SIZE));268 hi->vpn2 = ADDR2VPN2(ALIGN_DOWN(addr, PAGE_SIZE)); 278 269 hi->asid = asid; 279 270 } … … 304 295 305 296 printf("%-4u %-6u %0#10x %-#6x %1u%1u%1u%1u %0#10x\n", 306 i, hi.asid, HI_VPN22ADDR(hi.vpn2), mask.mask,307 lo0.g, lo0.v, lo0.d, lo0.c, LO_PFN2ADDR(lo0.pfn));297 i, hi.asid, VPN22ADDR(hi.vpn2), mask.mask, 298 lo0.g, lo0.v, lo0.d, lo0.c, PFN2ADDR(lo0.pfn)); 308 299 printf(" %1u%1u%1u%1u %0#10x\n", 309 lo1.g, lo1.v, lo1.d, lo1.c, LO_PFN2ADDR(lo1.pfn));300 lo1.g, lo1.v, lo1.d, lo1.c, PFN2ADDR(lo1.pfn)); 310 301 } 311 302
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