Changeset 5b65205 in mainline


Ignore:
Timestamp:
2005-11-08T11:53:45Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
389f41e
Parents:
6bc4dbd
Message:

ia64 work.
Add missing srlz_d().
Remove extra stops.
Coding style cleanups.

Location:
arch/ia64/src
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • arch/ia64/src/drivers/it.c

    r6bc4dbd r5b65205  
    4646        itv.m = 0;
    4747        itv_write(itv.value);
    48         srlz_d();
    4948
    5049        /* set Interval Timer Counter to zero */
    5150        itc_write(0);
    52         srlz_d();
    5351       
    5452        /* generate first Interval Timer interrupt in IT_DELTA ticks */
    5553        itm_write(IT_DELTA);
     54
     55        /* propagate changes */
    5656        srlz_d();
    5757}
     
    6262        eoi_write(EOI);
    6363        itm_write(itc_read() + IT_DELTA);       /* program next interruption */
     64        srlz_d();                               /* propagate changes */
    6465        clock();
    6566}
  • arch/ia64/src/ivt.S

    r6bc4dbd r5b65205  
    4747 * Some steps are not fully supported yet (e.g. interruptions
    4848 * from userspace and floating-point context).
     49 *
     50 * @param offs Offset from the beginning of IVT.
     51 * @param handler Interrupt handler address.
    4952 */
    5053.macro HEAVYWEIGHT_HANDLER offs handler
     
    101104        st8 [r31] = r27, -8     /* save ar.rnat */
    102105        st8 [r31] = r28, -8     /* save ar.bspstore */
    103         st8 [r31] = r29         /* save ar.bsp */
     106        st8 [r31] = r29, -8     /* save ar.bsp */
    104107       
    105108        mov ar.rsc = r24        /* restore RSE's setting */
     
    256259heavyweight_handler_finalize:
    257260    /* 16. RSE switch to interrupted context */
    258 
    259 /********************************************************************************************/
    260 
    261 
    262 
    263261        .auto
    264         cover                   /*Allocate zerro size frame (Step 1(from Intel Docs))*/
     262        cover                   /* allocate zerro size frame (step 1 (from Intel Docs)) */
    265263
    266264        add r31 = STACK_SCRATCH_AREA_SIZE, r12
    267265
    268         mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
    269         ld8 r29 = [r31], +8     
     266        mov r28 = ar.bspstore   /* calculate loadrs (step 2) */
     267        ld8 r29 = [r31], +8     /* load ar.bsp */
    270268        sub r27 = r29 , r28
    271269        shl r27 = r27, 16
     
    276274        mov ar.rsc = r24        /* place RSE in enforced lazy mode */
    277275
    278 
    279 
    280         loadrs                  /*(Step 3)*/
    281 
    282 
    283                                 /*Read saved registers*/
    284         ld8 r28 = [r31], +8     /*ar.bspstore*/
    285         ld8 r27 = [r31], +8     /*ar.rnat*/
    286         ld8 r26 = [r31], +8     /*cr.ifs*/
    287         ld8 r25 = [r31], +8     /*ar.pfs*/
    288         ld8 r24 = [r31], +8     /*ar.rsc*/
    289 
    290 
    291         mov ar.bspstore = r28   /*(Step 4)*/
    292         mov ar.rnat = r27       /*(Step 5)*/
    293 
    294         mov ar.pfs = r25        /*(Step 6)*/
     276        loadrs                  /* (step 3) */
     277
     278        ld8 r28 = [r31], +8     /* load ar.bspstore */
     279        ld8 r27 = [r31], +8     /* load ar.rnat */
     280        ld8 r26 = [r31], +8     /* load cr.ifs */
     281        ld8 r25 = [r31], +8     /* load ar.pfs */
     282        ld8 r24 = [r31], +8     /* load ar.rsc */
     283
     284        mov ar.bspstore = r28   /* (step 4) */
     285        mov ar.rnat = r27       /* (step 5) */
     286
     287        mov ar.pfs = r25        /* (step 6) */
    295288        mov cr.ifs = r26       
    296289
    297         mov ar.rsc = r24        /*(Step 7)*/
    298 
    299 
     290        mov ar.rsc = r24        /* (step 7) */
    300291        .explicit       
    301292
    302 
    303 /********************************************************************************************/
    304 
    305 
    306 
    307293    /* 17. restore interruption state from memory stack */
    308 
    309         ld8 r28 = [r31] , +8 ;; /* load cr.ifa */               
    310         ld8 r27 = [r31] , +8 ;; /* load cr.isr */
    311         ld8 r26 = [r31] , +8 ;; /* load cr.iipa */
    312         ld8 r25 = [r31] , +8 ;; /* load cr.ipsr */
    313         ld8 r24 = [r31] , +8 ;; /* load cr.iip */
    314 
     294        ld8 r28 = [r31], +8 ;;  /* load cr.ifa */               
     295        ld8 r27 = [r31], +8 ;;  /* load cr.isr */
     296        ld8 r26 = [r31], +8 ;;  /* load cr.iipa */
     297        ld8 r25 = [r31], +8 ;;  /* load cr.ipsr */
     298        ld8 r24 = [r31], +8 ;;  /* load cr.iip */
    315299
    316300        mov cr.iip = r24
     
    320304        mov cr.ifa = r28
    321305
    322 
    323        
    324306    /* 18. restore predicate registers from memory stack */
    325 
    326 
    327307        ld8 r29 = [r31] , -8 ;; /* load predicate registers */
    328         mov pr =r29 ;;
    329        
    330         add r12 = STACK_FRAME_SIZE,r12;;
     308        mov pr = r29
    331309       
    332310    /* 19. return from interruption */
    333         rfi;;
    334 
     311        add r12 = STACK_FRAME_SIZE, r12
     312        rfi ;;
    335313
    336314dump_gregs:
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