Changeset 5eb90cb in mainline
- Timestamp:
- 2009-03-17T20:33:29Z (16 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f3f7009
- Parents:
- e16e0d59
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/src/mm/page.c
re16e0d59 r5eb90cb 43 43 #include <config.h> 44 44 45 #ifdef CONFIG_SMP46 /** Entries locked in DTLB of BSP.47 *48 * Application processors need to have the same locked entries in their DTLBs as49 * the bootstrap processor.50 */51 static struct {52 uintptr_t virt_page;53 uintptr_t phys_page;54 int pagesize_code;55 } bsp_locked_dtlb_entry[DTLB_MAX_LOCKED_ENTRIES];56 57 /** Number of entries in bsp_locked_dtlb_entry array. */58 static count_t bsp_locked_dtlb_entries = 0;59 #endif /* CONFIG_SMP */60 61 45 /** Perform sparc64 specific initialization of paging. */ 62 46 void page_arch_init(void) … … 64 48 if (config.cpu_active == 1) { 65 49 page_mapping_operations = &ht_mapping_operations; 66 } else {67 68 #ifdef CONFIG_SMP69 unsigned int i;70 71 /*72 * Copy locked DTLB entries from the BSP.73 */74 for (i = 0; i < bsp_locked_dtlb_entries; i++) {75 dtlb_insert_mapping(bsp_locked_dtlb_entry[i].virt_page,76 bsp_locked_dtlb_entry[i].phys_page,77 bsp_locked_dtlb_entry[i].pagesize_code, true,78 false);79 }80 #endif81 82 50 } 83 51 } … … 98 66 uintptr_t hw_map(uintptr_t physaddr, size_t size) 99 67 { 100 unsigned int order; 101 unsigned int i; 102 103 ASSERT(config.cpu_active == 1); 104 105 struct { 106 int pagesize_code; 107 size_t increment; 108 count_t count; 109 } sizemap[] = { 110 { PAGESIZE_8K, 0, 1 }, /* 8K */ 111 { PAGESIZE_8K, MMU_PAGE_SIZE, 2 }, /* 16K */ 112 { PAGESIZE_8K, MMU_PAGE_SIZE, 4 }, /* 32K */ 113 { PAGESIZE_64K, 0, 1}, /* 64K */ 114 { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 2 }, /* 128K */ 115 { PAGESIZE_64K, 8 * MMU_PAGE_SIZE, 4 }, /* 256K */ 116 { PAGESIZE_512K, 0, 1 }, /* 512K */ 117 { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 2 }, /* 1M */ 118 { PAGESIZE_512K, 64 * MMU_PAGE_SIZE, 4 }, /* 2M */ 119 { PAGESIZE_4M, 0, 1 }, /* 4M */ 120 { PAGESIZE_4M, 512 * MMU_PAGE_SIZE, 2 } /* 8M */ 121 }; 122 123 ASSERT(ALIGN_UP(physaddr, MMU_PAGE_SIZE) == physaddr); 124 ASSERT(size <= 8 * 1024 * 1024); 125 126 if (size <= MMU_FRAME_SIZE) 127 order = 0; 128 else 129 order = (fnzb64(size - 1) + 1) - MMU_FRAME_WIDTH; 130 131 /* 132 * Use virtual addresses that are beyond the limit of physical memory. 133 * Thus, the physical address space will not be wasted by holes created 134 * by frame_alloc(). 135 */ 136 ASSERT(PA2KA(last_frame)); 137 uintptr_t virtaddr = ALIGN_UP(PA2KA(last_frame), 138 1 << (order + FRAME_WIDTH)); 139 last_frame = ALIGN_UP(KA2PA(virtaddr) + size, 140 1 << (order + FRAME_WIDTH)); 141 142 for (i = 0; i < sizemap[order].count; i++) { 143 /* 144 * First, insert the mapping into DTLB. 145 */ 146 dtlb_insert_mapping(virtaddr + i * sizemap[order].increment, 147 physaddr + i * sizemap[order].increment, 148 sizemap[order].pagesize_code, true, false); 149 150 #ifdef CONFIG_SMP 151 /* 152 * Second, save the information about the mapping for APs. 153 */ 154 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].virt_page = 155 virtaddr + i * sizemap[order].increment; 156 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].phys_page = 157 physaddr + i * sizemap[order].increment; 158 bsp_locked_dtlb_entry[bsp_locked_dtlb_entries].pagesize_code = 159 sizemap[order].pagesize_code; 160 bsp_locked_dtlb_entries++; 161 #endif 162 } 163 164 return virtaddr; 68 return PA2KA(physaddr); 165 69 } 166 70 -
uspace/srv/obio/obio.c
re16e0d59 r5eb90cb 95 95 case BUS_CLEAR_INTERRUPT: 96 96 inr = IPC_GET_ARG1(call); 97 base_virt[OBIO_CIR(inr & INO_MASK)] = 0;97 base_virt[OBIO_CIR(inr) & INO_MASK] = 0; 98 98 ipc_answer_0(callid, EOK); 99 99 break;
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