Changeset 5f83634 in mainline
- Timestamp:
- 2010-07-12T16:45:05Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 6b1a85c
- Parents:
- bee2d4c (diff), 8078180 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 14 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/amd64/src/mm/page.c
rbee2d4c r5f83634 90 90 if (as_page_fault(page, access, istate) == AS_PF_FAULT) { 91 91 fault_if_from_uspace(istate, "Page fault: %#x.", page); 92 panic_memtrap(istate, access, page, "Page fault.");92 panic_memtrap(istate, access, page, NULL); 93 93 } 94 94 } -
kernel/arch/arm32/src/mm/page_fault.c
rbee2d4c r5f83634 183 183 if (ret == AS_PF_FAULT) { 184 184 fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); 185 panic_memtrap(istate, access, badvaddr, "Page fault.");185 panic_memtrap(istate, access, badvaddr, NULL); 186 186 } 187 187 } … … 198 198 199 199 if (ret == AS_PF_FAULT) { 200 panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, 201 "Page fault - prefetch_abort."); 200 fault_if_from_uspace(istate, 201 "Page fault - prefetch_abort: %#x.", istate->pc); 202 panic_memtrap(istate, PF_ACCESS_EXEC, istate->pc, NULL); 202 203 } 203 204 } -
kernel/arch/ia32/include/asm.h
rbee2d4c r5f83634 429 429 extern void asm_delay_loop(uint32_t); 430 430 extern void asm_fake_loop(uint32_t); 431 432 extern uintptr_t int_syscall; 431 433 432 434 extern uintptr_t int_0; -
kernel/arch/ia32/include/pm.h
rbee2d4c r5f83634 67 67 #define AR_CODE (3 << 3) 68 68 #define AR_WRITABLE (1 << 1) 69 #define AR_INTERRUPT (0x0e) 70 #define AR_TSS (0x09) 69 #define AR_INTERRUPT (0xe) 70 #define AR_TRAP (0xf) 71 #define AR_TSS (0x9) 71 72 72 73 #define DPL_KERNEL (PL_KERNEL << 5) -
kernel/arch/ia32/src/asm.S
rbee2d4c r5f83634 30 30 * 31 31 */ 32 33 /**34 * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int35 * has no error word and 1 means interrupt with error word36 *37 */38 #define ERROR_WORD_INTERRUPT_LIST 0x00027d0039 32 40 33 #include <arch/pm.h> … … 153 146 wrmsr 154 147 ret 155 156 /** Clear nested flag157 *158 */159 .macro CLEAR_NT_FLAG160 pushfl161 andl $0xffffbfff, (%esp)162 popfl163 .endm164 148 165 149 #define ISTATE_OFFSET_EDX 0 … … 266 250 sysexit /* return to userspace */ 267 251 252 /* 253 * This is the legacy syscall handler using the interrupt mechanism. 254 */ 255 .global int_syscall 256 int_syscall: 257 subl $(ISTATE_SOFT_SIZE + 4), %esp 258 259 /* 260 * Push syscall arguments onto the stack 261 * 262 * NOTE: The idea behind the order of arguments passed 263 * in registers is to use all scratch registers 264 * first and preserved registers next. An optimized 265 * libc syscall wrapper can make use of this setup. 266 * The istate structure is arranged in the way to support 267 * this idea. 268 * 269 */ 270 movl %eax, ISTATE_OFFSET_EAX(%esp) 271 movl %ebx, ISTATE_OFFSET_EBX(%esp) 272 movl %ecx, ISTATE_OFFSET_ECX(%esp) 273 movl %edx, ISTATE_OFFSET_EDX(%esp) 274 movl %edi, ISTATE_OFFSET_EDI(%esp) 275 movl %esi, ISTATE_OFFSET_ESI(%esp) 276 movl %ebp, ISTATE_OFFSET_EBP(%esp) 277 278 /* 279 * Save the selector registers. 280 */ 281 movl %gs, %ecx 282 movl %fs, %edx 283 284 movl %ecx, ISTATE_OFFSET_GS(%esp) 285 movl %edx, ISTATE_OFFSET_FS(%esp) 286 287 movl %es, %ecx 288 movl %ds, %edx 289 290 movl %ecx, ISTATE_OFFSET_ES(%esp) 291 movl %edx, ISTATE_OFFSET_DS(%esp) 292 293 /* 294 * Switch to kernel selectors. 295 */ 296 movl $16, %eax 297 movl %eax, %ds 298 movl %eax, %es 299 300 movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) 301 movl ISTATE_OFFSET_EIP(%esp), %eax 302 movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) 303 leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp 304 305 cld 306 307 /* Call syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax) */ 308 call syscall_handler 309 310 /* 311 * Restore the selector registers. 312 */ 313 movl ISTATE_OFFSET_GS(%esp), %ecx 314 movl ISTATE_OFFSET_FS(%esp), %edx 315 316 movl %ecx, %gs 317 movl %edx, %fs 318 319 movl ISTATE_OFFSET_ES(%esp), %ecx 320 movl ISTATE_OFFSET_DS(%esp), %edx 321 322 movl %ecx, %es 323 movl %edx, %ds 324 325 /* 326 * Restore the preserved registers the handler cloberred itself 327 * (i.e. EBP). 328 */ 329 movl ISTATE_OFFSET_EBP(%esp), %ebp 330 331 addl $(ISTATE_SOFT_SIZE + 4), %esp 332 iret 333 334 /** 335 * Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int 336 * has no error word and 1 means interrupt with error word 337 * 338 */ 339 #define ERROR_WORD_INTERRUPT_LIST 0x00027d00 340 268 341 /** Declare interrupt handlers 269 342 * … … 272 345 * 273 346 */ 274 275 347 .macro handler i 276 348 .global int_\i 277 349 int_\i: 278 .ifeq \i - 0x30 279 /* Syscall handler */ 280 subl $(ISTATE_SOFT_SIZE + 4), %esp 281 282 /* 283 * Push syscall arguments onto the stack 284 * 285 * NOTE: The idea behind the order of arguments passed 286 * in registers is to use all scratch registers 287 * first and preserved registers next. An optimized 288 * libc syscall wrapper can make use of this setup. 289 * The istate structure is arranged in the way to support 290 * this idea. 291 * 292 */ 293 movl %eax, ISTATE_OFFSET_EAX(%esp) 294 movl %ebx, ISTATE_OFFSET_EBX(%esp) 295 movl %ecx, ISTATE_OFFSET_ECX(%esp) 296 movl %edx, ISTATE_OFFSET_EDX(%esp) 297 movl %edi, ISTATE_OFFSET_EDI(%esp) 298 movl %esi, ISTATE_OFFSET_ESI(%esp) 299 movl %ebp, ISTATE_OFFSET_EBP(%esp) 300 301 /* 302 * Save the selector registers. 303 */ 304 movl %gs, %ecx 305 movl %fs, %edx 306 307 movl %ecx, ISTATE_OFFSET_GS(%esp) 308 movl %edx, ISTATE_OFFSET_FS(%esp) 309 310 movl %es, %ecx 311 movl %ds, %edx 312 313 movl %ecx, ISTATE_OFFSET_ES(%esp) 314 movl %edx, ISTATE_OFFSET_DS(%esp) 315 316 /* 317 * Switch to kernel selectors. 318 */ 319 movl $16, %eax 320 movl %eax, %ds 321 movl %eax, %es 322 323 movl $0, ISTATE_OFFSET_EBP_FRAME(%esp) 324 movl ISTATE_OFFSET_EIP(%esp), %eax 325 movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) 326 leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp 327 328 cld 329 sti 330 331 /* Call syscall_handler(edx, ecx, ebx, esi, edi, ebp, eax) */ 332 call syscall_handler 333 334 CLEAR_NT_FLAG 335 336 /* 337 * Restore the selector registers. 338 */ 339 movl ISTATE_OFFSET_GS(%esp), %ecx 340 movl ISTATE_OFFSET_FS(%esp), %edx 341 342 movl %ecx, %gs 343 movl %edx, %fs 344 345 movl ISTATE_OFFSET_ES(%esp), %ecx 346 movl ISTATE_OFFSET_DS(%esp), %edx 347 348 movl %ecx, %es 349 movl %edx, %ds 350 351 /* 352 * Restore the preserved registers the handler cloberred itself 353 * (i.e. EBP). 354 */ 355 movl ISTATE_OFFSET_EBP(%esp), %ebp 356 357 addl $(ISTATE_SOFT_SIZE + 4), %esp 358 iret 359 360 .else 361 /* 362 * This macro distinguishes between two versions of ia32 363 * exceptions. One version has error word and the other 364 * does not have it. The latter version fakes the error 365 * word on the stack so that the handlers and istate_t 366 * can be the same for both types. 367 */ 368 .iflt \i - 32 369 .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST 370 /* 371 * Exception with error word: do nothing 372 */ 373 .else 374 /* 375 * Exception without error word: fake up one 376 */ 377 pushl $0 378 .endif 350 /* 351 * This macro distinguishes between two versions of ia32 352 * exceptions. One version has error word and the other 353 * does not have it. The latter version fakes the error 354 * word on the stack so that the handlers and istate_t 355 * can be the same for both types. 356 */ 357 .iflt \i - 32 358 .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST 359 /* 360 * Exception with error word: do nothing 361 */ 379 362 .else 380 363 /* 381 * Interrupt: fake up one364 * Exception without error word: fake up one 382 365 */ 383 366 pushl $0 384 367 .endif 385 386 subl $ISTATE_SOFT_SIZE, %esp 387 368 .else 388 369 /* 389 * Save the general purpose registers.370 * Interrupt: fake up one 390 371 */ 391 movl %eax, ISTATE_OFFSET_EAX(%esp) 392 movl %ebx, ISTATE_OFFSET_EBX(%esp) 393 movl %ecx, ISTATE_OFFSET_ECX(%esp) 394 movl %edx, ISTATE_OFFSET_EDX(%esp) 395 movl %edi, ISTATE_OFFSET_EDI(%esp) 396 movl %esi, ISTATE_OFFSET_ESI(%esp) 397 movl %ebp, ISTATE_OFFSET_EBP(%esp) 398 399 /* 400 * Save the selector registers. 401 */ 402 movl %gs, %eax 403 movl %fs, %ebx 404 movl %es, %ecx 405 movl %ds, %edx 406 407 movl %eax, ISTATE_OFFSET_GS(%esp) 408 movl %ebx, ISTATE_OFFSET_FS(%esp) 409 movl %ecx, ISTATE_OFFSET_ES(%esp) 410 movl %edx, ISTATE_OFFSET_DS(%esp) 411 412 /* 413 * Switch to kernel selectors. 414 */ 415 movl $16, %eax 416 movl %eax, %ds 417 movl %eax, %es 418 419 /* 420 * Imitate a regular stack frame linkage. 421 * Stop stack traces here if we came from userspace. 422 */ 423 cmpl $8, ISTATE_OFFSET_CS(%esp) 424 jz 0f 425 xorl %ebp, %ebp 426 427 0: 428 429 movl %ebp, ISTATE_OFFSET_EBP_FRAME(%esp) 430 movl ISTATE_OFFSET_EIP(%esp), %eax 431 movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) 432 leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp 433 434 cld 435 436 pushl %esp /* pass istate address */ 437 pushl $(\i) /* pass intnum */ 438 439 /* Call exc_dispatch(intnum, istate) */ 440 call exc_dispatch 441 442 addl $8, %esp /* clear arguments from the stack */ 443 444 CLEAR_NT_FLAG 445 446 /* 447 * Restore the selector registers. 448 */ 449 movl ISTATE_OFFSET_GS(%esp), %eax 450 movl ISTATE_OFFSET_FS(%esp), %ebx 451 movl ISTATE_OFFSET_ES(%esp), %ecx 452 movl ISTATE_OFFSET_DS(%esp), %edx 453 454 movl %eax, %gs 455 movl %ebx, %fs 456 movl %ecx, %es 457 movl %edx, %ds 458 459 /* 460 * Restore the scratch registers and the preserved 461 * registers the handler cloberred itself 462 * (i.e. EBX and EBP). 463 */ 464 movl ISTATE_OFFSET_EAX(%esp), %eax 465 movl ISTATE_OFFSET_EBX(%esp), %ebx 466 movl ISTATE_OFFSET_ECX(%esp), %ecx 467 movl ISTATE_OFFSET_EDX(%esp), %edx 468 movl ISTATE_OFFSET_EBP(%esp), %ebp 469 470 addl $(ISTATE_SOFT_SIZE + 4), %esp 471 iret 472 372 pushl $0 473 373 .endif 374 375 subl $ISTATE_SOFT_SIZE, %esp 376 377 /* 378 * Save the general purpose registers. 379 */ 380 movl %eax, ISTATE_OFFSET_EAX(%esp) 381 movl %ebx, ISTATE_OFFSET_EBX(%esp) 382 movl %ecx, ISTATE_OFFSET_ECX(%esp) 383 movl %edx, ISTATE_OFFSET_EDX(%esp) 384 movl %edi, ISTATE_OFFSET_EDI(%esp) 385 movl %esi, ISTATE_OFFSET_ESI(%esp) 386 movl %ebp, ISTATE_OFFSET_EBP(%esp) 387 388 /* 389 * Save the selector registers. 390 */ 391 movl %gs, %ecx 392 movl %fs, %edx 393 394 movl %ecx, ISTATE_OFFSET_GS(%esp) 395 movl %edx, ISTATE_OFFSET_FS(%esp) 396 397 movl %es, %ecx 398 movl %ds, %edx 399 400 movl %ecx, ISTATE_OFFSET_ES(%esp) 401 movl %edx, ISTATE_OFFSET_DS(%esp) 402 403 /* 404 * Switch to kernel selectors. 405 */ 406 movl $16, %eax 407 movl %eax, %ds 408 movl %eax, %es 409 410 /* 411 * Imitate a regular stack frame linkage. 412 * Stop stack traces here if we came from userspace. 413 */ 414 xorl %eax, %eax 415 cmpl $8, ISTATE_OFFSET_CS(%esp) 416 cmovl %eax, %ebp 417 418 movl %ebp, ISTATE_OFFSET_EBP_FRAME(%esp) 419 movl ISTATE_OFFSET_EIP(%esp), %eax 420 movl %eax, ISTATE_OFFSET_EIP_FRAME(%esp) 421 leal ISTATE_OFFSET_EBP_FRAME(%esp), %ebp 422 423 cld 424 425 pushl %esp /* pass istate address */ 426 pushl $(\i) /* pass intnum */ 427 428 /* Call exc_dispatch(intnum, istate) */ 429 call exc_dispatch 430 431 addl $8, %esp /* clear arguments from the stack */ 432 433 /* 434 * Restore the selector registers. 435 */ 436 movl ISTATE_OFFSET_GS(%esp), %ecx 437 movl ISTATE_OFFSET_FS(%esp), %edx 438 439 movl %ecx, %gs 440 movl %edx, %fs 441 442 movl ISTATE_OFFSET_ES(%esp), %ecx 443 movl ISTATE_OFFSET_DS(%esp), %edx 444 445 movl %ecx, %es 446 movl %edx, %ds 447 448 /* 449 * Restore the scratch registers and the preserved 450 * registers the handler cloberred itself 451 * (i.e. EBP). 452 */ 453 movl ISTATE_OFFSET_EAX(%esp), %eax 454 movl ISTATE_OFFSET_ECX(%esp), %ecx 455 movl ISTATE_OFFSET_EDX(%esp), %edx 456 movl ISTATE_OFFSET_EBP(%esp), %ebp 457 458 addl $(ISTATE_SOFT_SIZE + 4), %esp 459 iret 474 460 .endm 475 461 -
kernel/arch/ia32/src/mm/page.c
rbee2d4c r5f83634 115 115 if (as_page_fault(page, access, istate) == AS_PF_FAULT) { 116 116 fault_if_from_uspace(istate, "Page fault: %#x.", page); 117 panic_memtrap(istate, access, page, "Page fault.");117 panic_memtrap(istate, access, page, NULL); 118 118 } 119 119 } -
kernel/arch/ia32/src/pm.c
rbee2d4c r5f83634 130 130 d->selector = gdtselector(KTEXT_DES); 131 131 132 d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */133 134 132 if (i == VECTOR_SYSCALL) { 135 133 /* 136 * The syscall interrupt gate must be calleable from137 * userland. 134 * The syscall trap gate must be callable from 135 * userland. Interrupts will remain enabled. 138 136 */ 139 d->access |= DPL_USER; 137 d->access = AR_PRESENT | AR_TRAP | DPL_USER; 138 } else { 139 /* 140 * Other interrupts use interrupt gates which 141 * disable interrupts. 142 */ 143 d->access = AR_PRESENT | AR_INTERRUPT; 140 144 } 141 145 } … … 206 210 idt_setoffset(d++, (uintptr_t) &int_62); 207 211 idt_setoffset(d++, (uintptr_t) &int_63); 212 213 idt_setoffset(&idt[VECTOR_SYSCALL], (uintptr_t) &int_syscall); 208 214 } 209 215 -
kernel/arch/ia64/src/mm/tlb.c
rbee2d4c r5f83634 500 500 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { 501 501 fault_if_from_uspace(istate, "Page fault at %p.", va); 502 panic_memtrap(istate, PF_ACCESS_EXEC, va, 503 "Page fault."); 502 panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); 504 503 } 505 504 } … … 622 621 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 623 622 fault_if_from_uspace(istate, "Page fault at %p.", va); 624 panic_memtrap(istate, PF_ACCESS_READ, va, 625 "Page fault."); 623 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 626 624 } 627 625 } … … 671 669 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { 672 670 fault_if_from_uspace(istate, "Page fault at %p.", va); 673 panic_memtrap(istate, PF_ACCESS_WRITE, va, 674 "Page fault."); 671 panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); 675 672 } 676 673 } … … 708 705 if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { 709 706 fault_if_from_uspace(istate, "Page fault at %p.", va); 710 panic_memtrap(istate, PF_ACCESS_EXEC, va, 711 "Page fault."); 707 panic_memtrap(istate, PF_ACCESS_EXEC, va, NULL); 712 708 } 713 709 } … … 745 741 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 746 742 fault_if_from_uspace(istate, "Page fault at %p.", va); 747 panic_memtrap(istate, PF_ACCESS_READ, va, 748 "Page fault."); 743 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 749 744 } 750 745 } … … 778 773 if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { 779 774 fault_if_from_uspace(istate, "Page fault at %p.", va); 780 panic_memtrap(istate, PF_ACCESS_WRITE, va, "Page fault.");775 panic_memtrap(istate, PF_ACCESS_WRITE, va, NULL); 781 776 } 782 777 page_table_unlock(AS, true); … … 818 813 if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { 819 814 fault_if_from_uspace(istate, "Page fault at %p.", va); 820 panic_memtrap(istate, PF_ACCESS_READ, va, 821 "Page fault."); 815 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, NULL); 822 816 } 823 817 } -
kernel/arch/mips32/src/mm/tlb.c
rbee2d4c r5f83634 324 324 325 325 fault_if_from_uspace(istate, "TLB Refill Exception on %p.", va); 326 panic_memtrap(istate, PF_ACCESS_ READ, va, "TLB Refill Exception.");326 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Refill Exception."); 327 327 } 328 328 … … 333 333 334 334 fault_if_from_uspace(istate, "TLB Invalid Exception on %p.", va); 335 panic_memtrap(istate, PF_ACCESS_ READ, va, "TLB Invalid Exception.");335 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, "TLB Invalid Exception."); 336 336 } 337 337 -
kernel/arch/ppc32/src/mm/tlb.c
rbee2d4c r5f83634 112 112 { 113 113 fault_if_from_uspace(istate, "PHT Refill Exception on %p.", badvaddr); 114 panic_memtrap(istate, PF_ACCESS_ READ, badvaddr,114 panic_memtrap(istate, PF_ACCESS_UNKNOWN, badvaddr, 115 115 "PHT Refill Exception."); 116 116 } -
kernel/arch/sparc64/src/mm/sun4u/tlb.c
rbee2d4c r5f83634 259 259 /* NULL access in kernel */ 260 260 do_fast_data_access_mmu_miss_fault(istate, tag, 261 "Dereferencing NULL pointer ");261 "Dereferencing NULL pointer."); 262 262 } else if (page_8k >= end_of_identity) { 263 263 /* … … 442 442 { 443 443 fault_if_from_uspace(istate, "%s, Address=%p.", str, va); 444 panic_memtrap(istate, PF_ACCESS_EXEC, va, "%s.",str);444 panic_memtrap(istate, PF_ACCESS_EXEC, va, str); 445 445 } 446 446 … … 453 453 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, 454 454 tag.context); 455 panic_memtrap(istate, PF_ACCESS_ READ, va, "%s.", str);455 panic_memtrap(istate, PF_ACCESS_UNKNOWN, va, str); 456 456 } 457 457 … … 464 464 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, va, 465 465 tag.context); 466 panic_memtrap(istate, PF_ACCESS_WRITE, va, "%s.",str);466 panic_memtrap(istate, PF_ACCESS_WRITE, va, str); 467 467 } 468 468 -
kernel/arch/sparc64/src/mm/sun4v/tlb.c
rbee2d4c r5f83634 359 359 { 360 360 fault_if_from_uspace(istate, "%s, Address=%p.", str, va); 361 panic_memtrap(istate, PF_ACCESS_EXEC, va, "%s.",str);361 panic_memtrap(istate, PF_ACCESS_EXEC, va, str); 362 362 } 363 363 … … 367 367 fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d).", str, 368 368 DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); 369 panic_memtrap(istate, PF_ACCESS_ READ, DMISS_ADDRESS(page_and_ctx),370 "%s.");369 panic_memtrap(istate, PF_ACCESS_UNKNOWN, DMISS_ADDRESS(page_and_ctx), 370 str); 371 371 } 372 372 … … 377 377 DMISS_ADDRESS(page_and_ctx), DMISS_CONTEXT(page_and_ctx)); 378 378 panic_memtrap(istate, PF_ACCESS_WRITE, DMISS_ADDRESS(page_and_ctx), 379 "%s.");379 str); 380 380 } 381 381 -
kernel/generic/include/mm/as.h
rbee2d4c r5f83634 171 171 PF_ACCESS_READ, 172 172 PF_ACCESS_WRITE, 173 PF_ACCESS_EXEC 173 PF_ACCESS_EXEC, 174 PF_ACCESS_UNKNOWN 174 175 } pf_access_t; 175 176 -
kernel/generic/src/debug/panic.c
rbee2d4c r5f83634 61 61 } else if (cat == PANIC_BADTRAP) { 62 62 printf("BAD TRAP %ld.\n", address); 63 if (fmt) { 64 vprintf(fmt, args); 65 printf("\n"); 66 } 63 67 } else if (cat == PANIC_MEMTRAP) { 64 68 printf("A BAD MEMORY ACCESS WHILE "); … … 72 76 printf("REFERENCING"); 73 77 printf(" ADDRESS %p.\n", address); 78 if (fmt) { 79 vprintf(fmt, args); 80 printf("\n"); 81 } 74 82 } else { 75 83 printf("THE FOLLOWING REASON:\n"); 76 84 vprintf(fmt, args); 85 printf("\n"); 77 86 } 78 87 va_end(args);
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