Changeset 60f6b7c in mainline for arch/ia64/src/cpu/cpu.c
- Timestamp:
- 2005-09-01T17:47:55Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 5a2e9bbb
- Parents:
- 38207b9
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia64/src/cpu/cpu.c
r38207b9 r60f6b7c 2 2 #include <print.h> 3 3 #include <panic.h> 4 #include <arch/types.h> 4 5 5 6 extern int IVT; … … 14 15 15 16 int *p=&IVT; 17 18 volatile __u64 hlp,hlp2; 16 19 17 20 18 __asm__ ( 21 int psr = 0x2000; 22 23 __asm__ volatile ( 19 24 "mov r15 = %0;;" 20 25 "mov cr2 = r15;;" 26 "mov psr.l = %1;;" 21 27 : 22 : "r" (p) 28 : "r" (p), "r" (psr) 23 29 : "r15" 24 30 ); 31 32 33 34 /*Switch register bank of regs r16 .. r31 to 1 It is automaticly cleared on exception*/ 35 __asm__ volatile ("bsw.1;;"); 36 25 37 26 38 }
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