Changeset 61b5cf0c in mainline
- Timestamp:
- 2013-01-06T23:24:44Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 813b024
- Parents:
- b4b3a4cb
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/fpu_context.c
rb4b3a4cb r61b5cf0c 66 66 CPACR_CP10_USER_ACCESS = CPACR_CP10_MASK, 67 67 CPACR_CP11_USER_ACCESS = CPACR_CP11_MASK, 68 NSACR_CP10_FLAG = 1 << 10, 69 NSACR_CP11_FLAG = 1 << 11, 68 70 }; 69 71 … … 133 135 } 134 136 137 /** Enable coprocessor access. Turn both non-secure mode bit and generic access. 138 * Cortex A8 Manual says: 139 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately 140 * after an update of the Coprocessor Access Control Register, see Memory 141 * Barriers in the ARM Architecture Reference Manual. You must not attempt to 142 * execute any instructions that are affected by the change of access rights 143 * between the IMB sequence and the register update." 144 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register 145 * 146 * @note do we need to call secure monitor here? 147 */ 135 148 static void fpu_enable_coprocessor_access() 136 149 { 150 uint32_t cpr; 151 asm volatile("MRC p15, 0, %0, c1, c1, 0" : "=r" (cpr)::); 152 if (cpr & 1) 153 printf("We are in unsecure state, we can't change access\n"); 154 155 /* Allow non-secure access */ 156 uint32_t nsacr; 157 asm volatile ("mrc p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::); 158 /* FPU needs access to coprocessor 10 and 11. 159 * Moreover, they need to have same access enabled */ 160 nsacr |= NSACR_CP10_FLAG | NSACR_CP11_FLAG; 161 asm volatile ("mcr p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::); 162 163 #ifdef MACHINE_beagleboardxm 164 asm volatile ("isb" ::: "memory" ); 165 #endif 166 167 /* Allow coprocessor access */ 137 168 uint32_t cpacr; 138 169 asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::); … … 142 173 cpacr |= CPACR_CP11_USER_ACCESS; 143 174 asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::); 175 176 #ifdef MACHINE_beagleboardxm 177 asm volatile ("isb" ::: "memory" ); 178 #endif 144 179 } 145 180
Note:
See TracChangeset
for help on using the changeset viewer.