Changeset 62e015f in mainline

Timestamp:

2005-12-03T20:31:53Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d7ac642

Parents:

060ce90

Message:

sparc64 work.
MMU ASI & virtual addresses definitions.

Location:

arch/sparc64/include/mm

Files:

• tlb.h (modified) (1 diff)
• tte.h (modified) (1 diff)

arch/sparc64/include/mm/tlb.h

@@ -32 +32 @@
 #include <arch/mm/tte.h>
 
+/** I-MMU ASIs. */
+#define ASI_IMMU                        0x50
+#define ASI_IMMU_TSB_8KB_PTR_REG        0x51    
+#define ASI_IMMU_TSB_64KB_PTR_REG       0x52
+#define ASI_ITLB_DATA_IN_REG            0x54
+#define ASI_ITLB_DATA_ACCESS_REG        0x55
+#define ASI_ITLB_TAG_READ_REG           0x56
+#define ASI_IMMU_DEMAP                  0x57
+
+/** Virtual Addresses within ASI_IMMU. */
+#define VA_IMMU_TAG_TARGET              0x0     /**< IMMU tag target register. */
+#define VA_IMMU_SFSR                    0x18    /**< IMMU sync fault status register. */
+#define VA_IMMU_TSB_BASE                0x28    /**< IMMU TSB base register. */
+#define VA_IMMU_TAG_ACCESS              0x30    /**< IMMU TLB tag access register. */
+
+/** D-MMU ASIs. */
+#define ASI_DMMU                        0x58
+#define ASI_DMMU_TSB_8KB_PTR_REG        0x59    
+#define ASI_DMMU_TSB_64KB_PTR_REG       0x5a
+#define ASI_DMMU_TSB_DIRECT_PTR_REG     0x5b
+#define ASI_DTLB_DATA_IN_REG            0x5c
+#define ASI_DTLB_DATA_ACCESS_REG        0x5d
+#define ASI_DTLB_TAG_READ_REG           0x5e
+#define ASI_DMMU_DEMAP                  0x5f
+
+/** Virtual Addresses within ASI_DMMU. */
+#define VA_DMMU_TAG_TARGET              0x0     /**< DMMU tag target register. */
+#define VA_PRIMARY_CONTEXT_REG          0x8     /**< DMMU primary context register. */
+#define VA_SECONDARY_CONTEXT_REG        0x10    /**< DMMU secondary context register. */
+#define VA_DMMU_SFSR                    0x18    /**< DMMU sync fault status register. */
+#define VA_DMMU_SFAR                    0x20    /**< DMMU sync fault address register. */
+#define VA_DMMU_TSB_BASE                0x28    /**< DMMU TSB base register. */
+#define VA_DMMU_TAG_ACCESS              0x30    /**< DMMU TLB tag access register. */
+#define VA_DMMU_VA_WATCHPOINT_REG       0x38    /**< DMMU VA data watchpoint register. */
+#define VA_DMMU_PA_WATCHPOINT_REG       0x40    /**< DMMU PA data watchpoint register. */
+
 /** I-/D-TLB Data In/Access Register type. */
 typedef tte_data_t tlb_data_t;

arch/sparc64/include/mm/tte.h

@@ -40 +40 @@
                 unsigned context : 13;  /**< Context identifier. */
                 unsigned : 6;           /**< Reserved. */
-                long va_tag : 42;       /**< Virtual Address Tag, bits 63:22. */
+                __u64 va_tag : 42;      /**< Virtual Address Tag, bits 63:22. */
         } __attribute__ ((packed));
 };