Changeset 64f6ef04 in mainline


Ignore:
Timestamp:
2010-06-27T23:54:45Z (15 years ago)
Author:
Martin Decky <martin@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
05e3cb8
Parents:
a1f60f3
Message:

amd64: create identity mapping of the first 8 GB of physical memory (instead of just 4 GB) during the bootstrap process
remove the crude on-demand identity mapping creation which could lead to livelocks (unmapping the page pointing to 0 MB physical while trying to map the page pointing to 4096 MB physical)

(currently the implementation is in no way closer to the ideal solution of ticket #3, but at least it allows to debug non-trivial cases of physical memory sizes > 4 GB during the approach to solving #3)

Location:
kernel/arch
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/amd64/include/interrupt.h

    ra1f60f3 r64f6ef04  
    117117extern void trap_virtual_disable_irqs(uint16_t irqmask);
    118118
    119 /* AMD64 - specific page handler */
    120 extern void ident_page_fault(unsigned int, istate_t *);
    121 
    122119#endif
    123120

  • kernel/arch/amd64/src/boot/boot.S

    ra1f60f3 r64f6ef04  
    263263#
    264264.macro ptl2gen cnt g
    265 .if \cnt
    266         ptl2gen "\cnt - 8" \g
    267         .quad ((\cnt - 8) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    268         .quad ((\cnt - 7) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    269         .quad ((\cnt - 6) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    270         .quad ((\cnt - 5) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    271         .quad ((\cnt - 4) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    272         .quad ((\cnt - 3) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    273         .quad ((\cnt - 2) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    274         .quad ((\cnt - 1) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
    275 .endif
     265        .if \cnt
     266                ptl2gen "\cnt - 8" \g
     267                .quad ((\cnt - 8) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     268                .quad ((\cnt - 7) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     269                .quad ((\cnt - 6) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     270                .quad ((\cnt - 5) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     271                .quad ((\cnt - 4) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     272                .quad ((\cnt - 3) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     273                .quad ((\cnt - 2) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     274                .quad ((\cnt - 1) * 0x200000) + (\g * 1024 * 1024 * 1024) | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
     275        .endif
    276276.endm
    277277
    278 # Page table for pages in the first gigabyte.
    279 .align 4096
    280 .global ptl_2_0g
     278# Page table for pages in the 1st gigabyte.
     279.align 4096
    281280ptl_2_0g:
    282281        ptl2gen 512 0
    283282
    284 # Page table for pages in the second gigabyte.
    285 .align 4096
    286 .global ptl_2_1g
     283# Page table for pages in the 2nd gigabyte.
     284.align 4096
    287285ptl_2_1g:
    288286        ptl2gen 512 1
    289287
    290 # Page table for pages in the third gigabyte.
    291 .align 4096
    292 .global ptl_2_2g
     288# Page table for pages in the 3rd gigabyte.
     289.align 4096
    293290ptl_2_2g:
    294291        ptl2gen 512 2
    295292
    296 # Page table for pages in the fourth gigabyte.
    297 .align 4096
    298 .global ptl_2_3g
     293# Page table for pages in the 4th gigabyte.
     294.align 4096
    299295ptl_2_3g:
    300296        ptl2gen 512 3
    301297
    302 .align 4096
    303 .global ptl_1
     298# Page table for pages in the 5th gigabyte.
     299.align 4096
     300ptl_2_4g:
     301        ptl2gen 512 3
     302
     303# Page table for pages in the 6th gigabyte.
     304.align 4096
     305ptl_2_5g:
     306        ptl2gen 512 3
     307
     308# Page table for pages in the 7th gigabyte.
     309.align 4096
     310ptl_2_6g:
     311        ptl2gen 512 3
     312
     313# Page table for pages in the 8th gigabyte.
     314.align 4096
     315ptl_2_7g:
     316        ptl2gen 512 3
     317
     318.align 4096
    304319ptl_1:
    305         # Identity mapping for [0; 4G)
     320        # Identity mapping for [0; 8G)
    306321        .quad ptl_2_0g + (PTL_WRITABLE | PTL_PRESENT)
    307322        .quad ptl_2_1g + (PTL_WRITABLE | PTL_PRESENT)
    308323        .quad ptl_2_2g + (PTL_WRITABLE | PTL_PRESENT)
    309324        .quad ptl_2_3g + (PTL_WRITABLE | PTL_PRESENT)
    310         .fill 508, 8, 0
     325        .quad ptl_2_4g + (PTL_WRITABLE | PTL_PRESENT)
     326        .quad ptl_2_5g + (PTL_WRITABLE | PTL_PRESENT)
     327        .quad ptl_2_6g + (PTL_WRITABLE | PTL_PRESENT)
     328        .quad ptl_2_7g + (PTL_WRITABLE | PTL_PRESENT)
     329        .fill 504, 8, 0
    311330
    312331.align 4096

  • kernel/arch/amd64/src/interrupt.c

    ra1f60f3 r64f6ef04  
    214214        exc_register(12, "ss_fault", true, (iroutine_t) ss_fault);
    215215        exc_register(13, "gp_fault", true, (iroutine_t) gp_fault);
    216         exc_register(14, "ident_mapper", true, (iroutine_t) ident_page_fault);
    217216       
    218217#ifdef CONFIG_SMP

  • kernel/arch/amd64/src/mm/page.c

    ra1f60f3 r64f6ef04  
    3939#include <mm/frame.h>
    4040#include <mm/as.h>
    41 #include <arch/interrupt.h>
    4241#include <arch/asm.h>
    4342#include <config.h>
    … …  
    4746#include <panic.h>
    4847#include <align.h>
    49 
    50 /* Definitions for identity page mapper */
    51 pte_t helper_ptl1[512] __attribute__((aligned (PAGE_SIZE)));
    52 pte_t helper_ptl2[512] __attribute__((aligned (PAGE_SIZE)));
    53 pte_t helper_ptl3[512] __attribute__((aligned (PAGE_SIZE)));
    54 
    55 static uintptr_t oldpage = 0;
    56 
    57 extern pte_t ptl_0;  /* From boot.S */
    58 
    59 #define PTL1_PRESENT(ptl0, page) \
    60         (!(GET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
    61 
    62 #define PTL2_PRESENT(ptl1, page) \
    63         (!(GET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
    64 
    65 #define PTL3_PRESENT(ptl2, page) \
    66         (!(GET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
    67 
    68 #define PTL1_ADDR(ptl0, page) \
    69         ((pte_t *) PA2KA(GET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page))))
    70 
    71 #define PTL2_ADDR(ptl1, page) \
    72         ((pte_t *) PA2KA(GET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page))))
    73 
    74 #define PTL3_ADDR(ptl2, page) \
    75         ((pte_t *) PA2KA(GET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page))))
    76 
    77 #define SETUP_PTL1(ptl0, page, tgt) \
    78         { \
    79                 SET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    80                 SET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    81         }
    82 
    83 #define SETUP_PTL2(ptl1, page, tgt) \
    84         { \
    85                 SET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    86                 SET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    87         }
    88 
    89 #define SETUP_PTL3(ptl2, page, tgt) \
    90         { \
    91                 SET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    92                 SET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    93         }
    94 
    95 #define SETUP_FRAME(ptl3, page, tgt) \
    96         { \
    97                 SET_FRAME_ADDRESS_ARCH(ptl3, PTL3_INDEX_ARCH(page), (uintptr_t)KA2PA(tgt)); \
    98                 SET_FRAME_FLAGS_ARCH(ptl3, PTL3_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
    99         }
    10048
    10149void page_arch_init(void)
    … …  
    12270        } else
    12371                write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
    124 }
    125 
    126 /** Identity page mapper
    127  *
    128  * We need to map whole physical memory identically before the page subsystem
    129  * is initializaed. This thing clears page table and fills in the specific
    130  * items.
    131  *
    132  */
    133 void ident_page_fault(unsigned int n, istate_t *istate)
    134 {
    135         pte_t *aptl_1;
    136         pte_t *aptl_2;
    137         pte_t *aptl_3;
    138        
    139         uintptr_t page = read_cr2();
    140        
    141         /* Unmap old address */
    142         if (oldpage) {
    143                 pte_t *aptl_1 = PTL1_ADDR(&ptl_0, oldpage);
    144                 pte_t *aptl_2 = PTL2_ADDR(aptl_1, oldpage);
    145                 pte_t *aptl_3 = PTL3_ADDR(aptl_2, oldpage);
    146                
    147                 SET_FRAME_FLAGS_ARCH(aptl_3, PTL3_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
    148                
    149                 if (KA2PA(aptl_3) == KA2PA(helper_ptl3))
    150                         SET_PTL3_FLAGS_ARCH(aptl_2, PTL2_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
    151                
    152                 if (KA2PA(aptl_2) == KA2PA(helper_ptl2))
    153                         SET_PTL2_FLAGS_ARCH(aptl_1, PTL1_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
    154                
    155                 if (KA2PA(aptl_1) == KA2PA(helper_ptl1))
    156                         SET_PTL1_FLAGS_ARCH(&ptl_0, PTL0_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
    157         }
    158        
    159         if (PTL1_PRESENT(&ptl_0, page))
    160                 aptl_1 = PTL1_ADDR(&ptl_0, page);
    161         else {
    162                 SETUP_PTL1(&ptl_0, page, helper_ptl1);
    163                 aptl_1 = helper_ptl1;
    164         }
    165        
    166         if (PTL2_PRESENT(aptl_1, page))
    167                 aptl_2 = PTL2_ADDR(aptl_1, page);
    168         else {
    169                 SETUP_PTL2(aptl_1, page, helper_ptl2);
    170                 aptl_2 = helper_ptl2;
    171         }
    172        
    173         if (PTL3_PRESENT(aptl_2, page))
    174                 aptl_3 = PTL3_ADDR(aptl_2, page);
    175         else {
    176                 SETUP_PTL3(aptl_2, page, helper_ptl3);
    177                 aptl_3 = helper_ptl3;
    178         }
    179        
    180         SETUP_FRAME(aptl_3, page, page);
    181        
    182         oldpage = page;
    18372}
    18473

  • kernel/arch/ia32/src/mm/frame.c

    ra1f60f3 r64f6ef04  
    4747#include <print.h>
    4848
    49 #define PHYSMEM_LIMIT32  0x7c000000ull
    50 #define PHYSMEM_LIMIT64  0xe0000000ull
     49#define PHYSMEM_LIMIT32  0x07c000000ull
     50#define PHYSMEM_LIMIT64  0x200000000ull
    5151
    5252size_t hardcoded_unmapped_ktext_size = 0;
    … …  
    9696                 * or clip zones which go beyond PHYSMEM_LIMIT64.
    9797                 *
    98                  * The limit PHYSMEM_LIMIT64 (3.5 GB) is caused
    99                  * by various limitations of the current kernel
    100                  * memory management.
     98                 * The PHYSMEM_LIMIT64 (8 GB) is the size of the
     99                 * fixed 1:1 identically mapped physical memory
     100                 * accessible during the bootstrap process.
     101                 * This is a severe limitation of the current
     102                 * kernel memory management.
    101103                 *
    102104                 */
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