Changeset 65eac7b in mainline
- Timestamp:
- 2012-02-24T03:08:24Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 668a2e8
- Parents:
- 4e30369
- Location:
- uspace/drv/bus/usb/ohci
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ohci/hc.c
r4e30369 r65eac7b 515 515 516 516 /* Enable queues */ 517 //OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));518 //usb_log_debug("Queues enabled(%x).\n",519 //OHCI_RD(instance->registers->control));517 OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE)); 518 usb_log_debug("Queues enabled(%x).\n", 519 OHCI_RD(instance->registers->control)); 520 520 521 521 /* Enable interrupts */ … … 596 596 597 597 for (unsigned i = 0; i < 32; ++i) { 598 instance->hcca->int_ep[i] =599 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa ;598 OHCI_WR(instance->hcca->int_ep[i], 599 instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa); 600 600 } 601 601 usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n", -
uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c
r4e30369 r65eac7b 58 58 /* Mark as dead, used for dummy EDs at the beginning of 59 59 * endpoint lists. */ 60 instance->status = ED_STATUS_K_FLAG;60 OHCI_WR(instance->status, ED_STATUS_K_FLAG); 61 61 return; 62 62 } … … 65 65 66 66 /* Status: address, endpoint nr, direction mask and max packet size. */ 67 instance->status = 068 |((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT)67 OHCI_WR(instance->status, 68 ((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT) 69 69 | ((ep->endpoint & ED_STATUS_EN_MASK) << ED_STATUS_EN_SHIFT) 70 70 | ((dir[ep->direction] & ED_STATUS_D_MASK) << ED_STATUS_D_SHIFT) 71 71 | ((ep->max_packet_size & ED_STATUS_MPS_MASK) 72 << ED_STATUS_MPS_SHIFT) ;72 << ED_STATUS_MPS_SHIFT)); 73 73 74 74 /* Low speed flag */ 75 75 if (ep->speed == USB_SPEED_LOW) 76 instance->status |= ED_STATUS_S_FLAG;76 OHCI_SET(instance->status, ED_STATUS_S_FLAG); 77 77 78 78 /* Isochronous format flag */ 79 79 if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS) 80 instance->status |= ED_STATUS_F_FLAG;80 OHCI_SET(instance->status, ED_STATUS_F_FLAG); 81 81 82 82 /* Set TD to the list */ 83 83 const uintptr_t pa = addr_to_phys(td); 84 instance->td_head = pa & ED_TDHEAD_PTR_MASK;85 instance->td_tail = pa & ED_TDTAIL_PTR_MASK;84 OHCI_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK); 85 OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); 86 86 87 87 /* Set toggle bit */ 88 88 if (ep->toggle) 89 instance->td_head |= ED_TDHEAD_TOGGLE_CARRY;89 OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); 90 90 91 91 } -
uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h
r4e30369 r65eac7b 40 40 #include <usb/host/endpoint.h> 41 41 42 #include "../ohci_regs.h" 42 43 #include "../utils/malloc32.h" 43 44 #include "transfer_descriptor.h" … … 116 117 { 117 118 assert(instance); 118 return (instance->td_head & ED_TDHEAD_HALTED_FLAG) 119 || (instance->status & ED_STATUS_K_FLAG); 119 return (OHCI_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG) 120 || (OHCI_RD(instance->status) & ED_STATUS_K_FLAG); 121 } 122 123 static inline void ed_clear_halt(ed_t *instance) 124 { 125 assert(instance); 126 OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); 120 127 } 121 128 … … 128 135 { 129 136 assert(instance); 130 return ( instance->td_head& ED_TDHEAD_PTR_MASK)131 != ( instance->td_tail& ED_TDTAIL_PTR_MASK);137 return (OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK) 138 != (OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK); 132 139 } 133 140 … … 141 148 assert(instance); 142 149 const uintptr_t pa = addr_to_phys(td); 143 instance->td_tail = pa & ED_TDTAIL_PTR_MASK; 150 OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK); 151 } 152 153 static inline uint32_t ed_tail_td(const ed_t *instance) 154 { 155 assert(instance); 156 return OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK; 157 } 158 159 static inline uint32_t ed_head_td(const ed_t *instance) 160 { 161 assert(instance); 162 return OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK; 144 163 } 145 164 … … 155 174 const uint32_t pa = addr_to_phys(next); 156 175 assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa); 157 instance->next = pa;176 OHCI_WR(instance->next, pa); 158 177 } 159 178 … … 166 185 { 167 186 assert(instance); 168 return ( instance->td_head& ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;187 return (OHCI_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0; 169 188 } 170 189 … … 178 197 assert(instance); 179 198 if (toggle) { 180 instance->td_head |= ED_TDHEAD_TOGGLE_CARRY;199 OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); 181 200 } else { 182 201 /* Clear halted flag when reseting toggle TODO: Why? */ 183 instance->td_head &= ~ED_TDHEAD_TOGGLE_CARRY;184 instance->td_head &= ~ED_TDHEAD_HALTED_FLAG;202 OHCI_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY); 203 OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG); 185 204 } 186 205 } -
uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c
r4e30369 r65eac7b 33 33 */ 34 34 #include <usb/usb.h> 35 #include <mem.h> 36 #include "../utils/malloc32.h" 35 37 #include "transfer_descriptor.h" 36 38 … … 58 60 bzero(instance, sizeof(td_t)); 59 61 /* Set PID and Error code */ 60 instance->status = 061 |((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT)62 | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT) ;62 OHCI_WR(instance->status, 63 ((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT) 64 | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT)); 63 65 64 66 if (toggle == 0 || toggle == 1) { 65 67 /* Set explicit toggle bit */ 66 instance->status |= TD_STATUS_T_USE_TD_FLAG;67 instance->status |= toggle ? TD_STATUS_T_FLAG : 0;68 OHCI_SET(instance->status, TD_STATUS_T_USE_TD_FLAG); 69 OHCI_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0); 68 70 } 69 71 70 72 /* Alow less data on input. */ 71 73 if (dir == USB_DIRECTION_IN) { 72 instance->status |= TD_STATUS_ROUND_FLAG;74 OHCI_SET(instance->status, TD_STATUS_ROUND_FLAG); 73 75 } 74 76 75 77 if (buffer != NULL) { 76 78 assert(size != 0); 77 instance->cbp = addr_to_phys(buffer);78 instance->be = addr_to_phys(buffer + size - 1);79 OHCI_WR(instance->cbp, addr_to_phys(buffer)); 80 OHCI_WR(instance->be, addr_to_phys(buffer + size - 1)); 79 81 } 80 82 81 instance->next = addr_to_phys(next) & TD_NEXT_PTR_MASK;83 OHCI_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK); 82 84 83 85 } -
uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h
r4e30369 r65eac7b 38 38 #include <stdint.h> 39 39 40 #include "../ utils/malloc32.h"40 #include "../ohci_regs.h" 41 41 #include "completion_codes.h" 42 42 … … 100 100 { 101 101 assert(instance); 102 const int cc = 103 (instance->status>> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;102 const int cc =(OHCI_RD(instance->status) 103 >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK; 104 104 /* This value is changed on transfer completion, 105 105 * either to CC_NOERROR or and error code. … … 119 119 { 120 120 assert(instance); 121 const int cc = 122 (instance->status>> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;121 const int cc = (OHCI_RD(instance->status) 122 >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK; 123 123 return cc_to_rc(cc); 124 124 } … … 136 136 return 0; 137 137 /* Buffer end points to the last byte of transfer buffer, so add 1 */ 138 return instance->be - instance->cbp+ 1;138 return OHCI_RD(instance->be) - OHCI_RD(instance->cbp) + 1; 139 139 } 140 140 #endif -
uspace/drv/bus/usb/ohci/ohci_batch.c
r4e30369 r65eac7b 231 231 232 232 /* Check TD assumption */ 233 const uint32_t pa = 234 addr_to_phys(ohci_batch->tds[leave_td]); 235 assert((ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK) 236 == pa); 237 233 assert(ed_head_td(ohci_batch->ed) == 234 addr_to_phys(ohci_batch->tds[leave_td])); 235 236 /* Set tail to the same TD */ 238 237 ed_set_tail_td(ohci_batch->ed, 239 238 ohci_batch->tds[leave_td]); 240 239 241 240 /* Clear possible ED HALT */ 242 ohci_batch->ed->td_head &= ~ED_TDHEAD_HALTED_FLAG;241 ed_clear_halt(ohci_batch->ed); 243 242 break; 244 243 } … … 253 252 254 253 /* Make sure that we are leaving the right TD behind */ 255 const uint32_t pa = addr_to_phys(ohci_ep->td); 256 assert(pa == (ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK)); 257 assert(pa == (ohci_batch->ed->td_tail & ED_TDTAIL_PTR_MASK)); 254 assert(addr_to_phys(ohci_ep->td) == ed_head_td(ohci_batch->ed)); 255 assert(addr_to_phys(ohci_ep->td) == ed_tail_td(ohci_batch->ed)); 256 // const uint32_t pa = addr_to_phys(ohci_ep->td); 257 // assert(pa == (ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK)); 258 // assert(pa == (ohci_batch->ed->td_tail & ED_TDTAIL_PTR_MASK)); 258 259 259 260 return true;
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