Changes in / [5fcd537:660e8fa] in mainline


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  • HelenOS.config

    r5fcd537 r660e8fa  
    8787
    8888% CPU type
    89 @ "cortex_a8" ARM Cortex A-8
     89@ "armv4" ARMv4
     90! [PLATFORM=arm32&(MACHINE=gta02)] PROCESSOR (choice)
     91
     92% CPU type
     93@ "armv5" ARMv5
     94! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
     95
     96% CPU type
     97@ "armv7_a" ARMv7-A
    9098! [PLATFORM=arm32&MACHINE=beagleboardxm] PROCESSOR (choice)
    91 
    92 % CPU type
    93 @ "arm920t" ARM920T
    94 ! [PLATFORM=arm32&MACHINE=gta02] PROCESSOR (choice)
    95 
    96 % CPU type
    97 @ "arm926ej_s" ARM926EJ-S
    98 ! [PLATFORM=arm32&MACHINE=integratorcp] PROCESSOR (choice)
    99 
    100 
    101 # Add more ARMv4 CPUs
    102 % CPU arch
    103 @ "armv4" ARMv4
    104 ! [PLATFORM=arm32&(PROCESSOR=arm920t)] PROCESSOR_ARCH (choice)
    105 
    106 # Add more ARMv5 CPUs
    107 % CPU arch
    108 @ "armv5" ARMv5
    109 ! [PLATFORM=arm32&(PROCESSOR=arm926ej_s)] PROCESSOR_ARCH (choice)
    110 
    111 # Add more ARMv7-A CPUs
    112 % CPU arch
    113 @ "armv7_a" ARMv7-A
    114 ! [PLATFORM=arm32&(PROCESSOR=cortex_a8)] PROCESSOR_ARCH (choice)
    11599
    116100% RAM disk format
    … …  
    364348## armv7 made fpu hardware compulsory
    365349% FPU support
    366 ! [PLATFORM=arm32&PROCESSOR_ARCH=armv7_a] CONFIG_FPU (y)
     350! [PLATFORM=arm32&PROCESSOR=armv7_a] CONFIG_FPU (y)
    367351
    368352% FPU support

  • boot/arch/arm32/Makefile.inc

    r5fcd537 r660e8fa  
    4949BITS = 32
    5050ENDIANESS = LE
    51 EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
     51EXTRA_CFLAGS = -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
    5252
    5353ifeq ($(MACHINE), gta02)

  • boot/arch/arm32/include/mm.h

    r5fcd537 r660e8fa  
    5858#define GTA02_IOMEM_END  0x60000000
    5959
    60 /** Start of ram memory on BBxM */
    61 #define BBXM_RAM_START   0x80000000
    62 /** Start of ram memory on BBxM */
    63 #define BBXM_RAM_END   0xc0000000
    64 
    65 
    6660/* Page table level 0 entry - "section" format is used
    6761 * (one-level paging, 1 MB sized pages). Used only while booting the kernel.

  • boot/arch/arm32/src/mm.c

    r5fcd537 r660e8fa  
    5656        else
    5757                return 1;
    58 #elif defined MACHINE_beagleboardxm
    59         const unsigned long address = section << PTE_SECTION_SHIFT;
    60         if (address >= BBXM_RAM_START && address < BBXM_RAM_END)
    61                 return 1;
     58#else
     59        return 0;
    6260#endif
    63         return 0;
    6461}
    6562
    … …  
    133130                "mcr p15, 0, r0, c3, c0, 0\n"
    134131               
    135 #ifdef PROCESSOR_ARCH_armv7_a
    136                 /* armv7 no longer requires cache entries to be invalid
    137                  * upon reset, do this manually */
    138                 /* Invalidate ICache */
    139                 "mcr p15, 0, r0, c7, c5, 6\n"
    140                 //TODO: Invalidate data cache
     132#ifdef PROCESSOR_armv7_a
     133                /* Read Auxiliary control register */
     134                "mrc p15, 0, r0, c1, c0, 1\n"
     135                /* Mask to enable L2 cache */
     136                "ldr r1, =0x00000002\n"
     137                "orr r0, r0, r1\n"
     138                /* Store Auxiliary control register */
     139                "mrc p15, 0, r0, c1, c0, 1\n"
    141140#endif
    142 
    143141                /* Current settings */
    144142                "mrc p15, 0, r0, c1, c0, 0\n"
    145143               
    146 #if defined(PROCESSOR_cortex_a8) | defined(MACHINE_gta02)
    147                 /* Mask to enable paging, I-cache D-cache and branch predict
    148                  * See kernel/arch/arm32/include/regutils.h for bit values.
    149                  * It's safe because Cortex-A8 implements IVIPT extension
    150                  * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245).
    151                  * It's safe for gta02 too because we turn the caches off
    152                  * before switching to kernel. */
    153                 "ldr r1, =0x00001805\n"
    154 #elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
    155                 /* Enable paging, data cache and branch prediction
    156                  * see arch/arm32/src/cpu/cpu.c for reasoning */
    157                 "ldr r1, =0x00000805\n"
     144#ifdef PROCESSOR_armv7_a
     145                /* Mask to enable paging, caching */
     146                "ldr r1, =0x00000005\n"
     147#else
     148#ifdef MACHINE_gta02
     149                /* Mask to enable paging (bit 0),
     150                   D-cache (bit 2), I-cache (bit 12) */
     151                "ldr r1, =0x00001005\n"
    158152#else
    159153                /* Mask to enable paging */
    160154                "ldr r1, =0x00000001\n"
     155#endif
    161156#endif
    162157                "orr r0, r0, r1\n"

  • kernel/arch/arm32/Makefile.inc

    r5fcd537 r660e8fa  
    3333ATSIGN = %
    3434
    35 GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH)) -mno-unaligned-access
     35GCC_CFLAGS += -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR)) -mno-unaligned-access
    3636
    3737ifeq ($(MACHINE),beagleboardxm)

  • kernel/arch/arm32/include/asm.h

    r5fcd537 r660e8fa  
    4848 * ARM920T has custom coprocessor action to do the same. See ARM920T Technical
    4949 * Reference Manual ch 4.9 p. 4-23 (103 in the PDF)
    50  * ARM926EJ-S uses the same coprocessor instruction as ARM920T. See ARM926EJ-S
    51  * chapter 2.3.8 p.2-22 (52 in the PDF)
    52  *
    53  * @note Although mcr p15, 0, R0, c7, c0, 4 is defined in ARM Architecture
    54  * reference manual for armv4/5 CP15 implementation is mandatory only for
    55  * armv6+.
    5650 */
    5751NO_TRACE static inline void cpu_sleep(void)
    5852{
    59 #ifdef PROCESSOR_ARCH_armv7_a
    60         asm volatile ( "wfe" );
    61 #elif defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_arm926ej_s) | defined(PROCESSOR_arm920t)
    62         asm volatile ( "mcr p15, 0, R0, c7, c0, 4" );
     53#ifdef PROCESSOR_armv7_a
     54        asm volatile ( "wfe" :: );
     55#elif defined(MACHINE_gta02)
     56        asm volatile ( "mcr p15,0,R0,c7,c0,4" :: );
    6357#endif
    6458}

  • kernel/arch/arm32/include/barrier.h

    r5fcd537 r660e8fa  
    6060#define read_barrier()    asm volatile ("dsb" ::: "memory")
    6161#define write_barrier()   asm volatile ("dsb st" ::: "memory")
    62 #elif defined PROCESSOR_ARCH_armv6
    63 /* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
    64  * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
    65  * CP15 implementation is mandatory only for armv6+.
    66  */
    67 #define memory_barrier()  asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory")
    68 #define read_barrier()    asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory")
    69 #define write_barrier()   read_barrier()
    7062#else
    71 /* Older manuals mention syscalls as a way to implement cache coherency and
    72  * barriers. See for example ARM Architecture Reference Manual Version D
    73  * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
    74  */
    75 // TODO implement on per PROCESSOR basis
    7663#define memory_barrier()  asm volatile ("" ::: "memory")
    7764#define read_barrier()    asm volatile ("" ::: "memory")
    7865#define write_barrier()   asm volatile ("" ::: "memory")
    7966#endif
    80 
    8167/*
    8268 * There are multiple ways ICache can be implemented on ARM machines. Namely

  • kernel/arch/arm32/include/mm/frame.h

    r5fcd537 r660e8fa  
    4747
    4848#ifdef MACHINE_gta02
    49 
    50 #define PHYSMEM_START_ADDR       0x30008000
    5149#define BOOT_PAGE_TABLE_ADDRESS  0x30010000
    52 
    5350#elif defined MACHINE_beagleboardxm
    54 
    55 #define PHYSMEM_START_ADDR       0x80000000
    5651#define BOOT_PAGE_TABLE_ADDRESS  0x80008000
    57 
    5852#else
    59 
    60 #define PHYSMEM_START_ADDR       0x00000000
    6153#define BOOT_PAGE_TABLE_ADDRESS  0x00008000
    62 
    6354#endif
    6455
    … …  
    6657#define BOOT_PAGE_TABLE_SIZE_IN_FRAMES  (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH)
    6758
     59#ifdef MACHINE_gta02
     60#define PHYSMEM_START_ADDR      0x30008000
     61#elif defined MACHINE_beagleboardxm
     62#define PHYSMEM_START_ADDR      0x80000000
     63#else
     64#define PHYSMEM_START_ADDR      0x00000000
     65#endif
    6866
    6967extern void frame_low_arch_init(void);

  • kernel/arch/arm32/include/mm/page.h

    r5fcd537 r660e8fa  
    129129        set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
    130130
    131 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
     131#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
    132132#include "page_armv6.h"
    133 #elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
     133#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    134134#include "page_armv4.h"
    135135#else

  • kernel/arch/arm32/include/regutils.h

    r5fcd537 r660e8fa  
    4747#define CP15_R1_CACHE_EN          (1 << 2)
    4848#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
    49 #define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only, big endian switch */
     49#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
    5050#define CP15_R1_SWAP_EN           (1 << 10)
    5151#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)

  • kernel/arch/arm32/src/cpu/cpu.c

    r5fcd537 r660e8fa  
    9898void cpu_arch_init(void)
    9999{
    100         /* Get rid of any boot code hiding in ICache
    101          * This is safe without regards to ICache state. */
    102         memory_barrier();
    103         smc_coherence();
    104 
     100#if defined(PROCESSOR_armv7_a) | defined(PROCESSOR_armv6)
    105101        uint32_t control_reg = 0;
    106102        asm volatile (
    … …  
    109105        );
    110106       
    111         /* Turn off tex remap, RAZ/WI prior to armv7 */
     107        /* Turn off tex remap, RAZ ignores writes prior to armv7 */
    112108        control_reg &= ~CP15_R1_TEX_REMAP_EN;
    113         /* Turn off accessed flag, RAZ/WI prior to armv7 */
     109        /* Turn off accessed flag, RAZ ignores writes prior to armv7 */
    114110        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
    115         /* Disable branch prediction RAZ/WI if not supported */
    116         control_reg &= ~CP15_R1_BRANCH_PREDICT_EN;
    117 
    118         /* Unaligned access is supported on armv6+ */
    119 #if defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
    120         /* Enable unaligned access, RAZ/WI prior to armv6
    121          * switchable on armv6, RAO/WI writes on armv7,
     111        /* Enable unaligned access, RAZ ignores writes prior to armv6
     112         * switchable on armv6, RAO ignores writes on armv7,
    122113         * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
    123114         * L.3.1 (p. 2456) */
    … …  
    133124         *    ARM Architecture Reference Manual ARMv7-A and ARMv7-R Edition
    134125         *    B3.11.1 (p. 1383)
    135          * We are safe to turn this on. For arm v6 see ch L.6.2 (p. 2469)
    136          * L2 Cache for armv7 was enabled in boot code.
     126         * ICache coherency is elaborate on in barrier.h.
     127         * We are safe to turn these on.
    137128         */
    138         control_reg |= CP15_R1_CACHE_EN;
    139 #endif
    140 #ifdef PROCESSOR_cortex_a8
    141          /* ICache coherency is elaborate on in barrier.h.
    142           * Cortex-A8 implements IVIPT extension.
    143           * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
    144         control_reg |= CP15_R1_INST_CACHE_EN;
    145 #endif
     129        control_reg |= CP15_R1_CACHE_EN | CP15_R1_INST_CACHE_EN;
    146130       
    147131        asm volatile (
    … …  
    149133                :: [control_reg] "r" (control_reg)
    150134        );
     135#endif
    151136#ifdef CONFIG_FPU
    152137        fpu_setup();

  • kernel/arch/arm32/src/fpu_context.c

    r5fcd537 r660e8fa  
    119119 * rely on user decision to use CONFIG_FPU.
    120120 */
    121 #ifdef PROCESSOR_ARC_armv7_a
     121#ifdef PROCESSOR_armv7_a
    122122        const uint32_t cpacr = CPACR_read();
    123123        /* FPU needs access to coprocessor 10 and 11.
    … …  
    148148 * rely on user decision to use CONFIG_FPU.
    149149 */
    150 #ifndef PROCESSOR_ARCH_armv7_a
     150#ifndef PROCESSOR_armv7_a
    151151        return;
    152152#endif

  • kernel/arch/arm32/src/mm/page_fault.c

    r5fcd537 r660e8fa  
    174174}
    175175
    176 #if defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
     176#if defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    177177/** Decides whether read or write into memory is requested.
    178178 *
    … …  
    281281        }
    282282
    283 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
     283#if defined(PROCESSOR_armv6) | defined(PROCESSOR_armv7_a)
    284284        const pf_access_t access =
    285285            fsr.data.wr ? PF_ACCESS_WRITE : PF_ACCESS_READ;
    286 #elif defined(PROCESSOR_ARCH_armv4) | defined(PROCESSOR_ARCH_armv5)
     286#elif defined(PROCESSOR_armv4) | defined(PROCESSOR_armv5)
    287287        const pf_access_t access = get_memory_access_type(istate->pc, badvaddr);
    288288#else

  • uspace/lib/c/arch/arm32/Makefile.common

    r5fcd537 r660e8fa  
    2828#
    2929
    30 GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR_ARCH))
     30GCC_CFLAGS += -ffixed-r9 -mtp=soft -fno-omit-frame-pointer -mapcs-frame -march=$(subst _,-,$(PROCESSOR))
    3131
    3232ifeq ($(CONFIG_FPU),y)
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