Changeset 6767c1d in mainline
- Timestamp:
- 2006-09-01T13:33:03Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9314ee1
- Parents:
- ed166f7
- Location:
- kernel/arch/sparc64
- Files:
-
- 7 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/trap/exception.h
red166f7 r6767c1d 43 43 44 44 #ifndef __ASM__ 45 extern void do_instruction_access_exc(void); 46 extern void do_mem_address_not_aligned(void); 47 extern void do_data_access_error(void); 48 extern void do_illegal_instruction(void); 45 46 #include <typedefs.h> 47 48 extern void do_instruction_access_exc(int n, istate_t *istate); 49 extern void do_mem_address_not_aligned(int n, istate_t *istate); 50 extern void do_data_access_error(int n, istate_t *istate); 51 extern void do_illegal_instruction(int n, istate_t *istate); 52 49 53 #endif /* !__ASM__ */ 50 54 … … 53 57 /** @} 54 58 */ 55 -
kernel/arch/sparc64/include/trap/interrupt.h
red166f7 r6767c1d 90 90 91 91 #ifndef __ASM__ 92 extern void interrupt( void);92 extern void interrupt(int n, istate_t *istate); 93 93 #endif /* !def __ASM__ */ 94 94 -
kernel/arch/sparc64/include/trap/mmu.h
red166f7 r6767c1d 54 54 55 55 .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER 56 !57 !First, try to refill TLB from TSB.58 !56 /* 57 * First, try to refill TLB from TSB. 58 */ 59 59 ! TODO 60 60 -
kernel/arch/sparc64/include/trap/trap_table.h
red166f7 r6767c1d 101 101 .endm 102 102 103 .macro SIMPLE_HANDLER f104 call \f105 nop106 .endm107 103 #endif /* __ASM__ */ 108 104 -
kernel/arch/sparc64/src/trap/exception.c
red166f7 r6767c1d 35 35 36 36 #include <arch/trap/exception.h> 37 #include <arch/interrupt.h> 37 38 #include <arch/asm.h> 38 39 #include <debug.h> 40 #include <typedefs.h> 39 41 40 42 /** Handle instruction_access_exception. */ 41 void do_instruction_access_exc( void)43 void do_instruction_access_exc(int n, istate_t *istate) 42 44 { 43 panic("Instruction Access Exception \n");45 panic("Instruction Access Exception at %p.\n", istate->tpc); 44 46 } 45 47 46 48 /** Handle mem_address_not_aligned. */ 47 void do_mem_address_not_aligned( void)49 void do_mem_address_not_aligned(int n, istate_t *istate) 48 50 { 49 panic("Memory Address Not Aligned \n");51 panic("Memory Address Not Aligned from %p.\n", istate->tpc); 50 52 } 51 53 52 54 /** Handle data_access_error. */ 53 void do_data_access_error( void)55 void do_data_access_error(int n, istate_t *istate) 54 56 { 55 panic("Data Access Error : %p\n", tpc_read());57 panic("Data Access Error from %p.\n", istate->tpc); 56 58 } 57 59 58 60 /** Handle mem_address_not_aligned. */ 59 void do_illegal_instruction( void)61 void do_illegal_instruction(int n, istate_t *istate) 60 62 { 61 panic("Illegal Instruction : %p\n", tpc_read());63 panic("Illegal Instruction at %p.\n", istate->tpc); 62 64 } 63 65 -
kernel/arch/sparc64/src/trap/interrupt.c
red166f7 r6767c1d 37 37 #include <interrupt.h> 38 38 #include <arch/drivers/fhc.h> 39 #include <typedefs.h> 39 40 #include <arch/types.h> 40 41 #include <debug.h> … … 65 66 } 66 67 67 void interrupt( void)68 void interrupt(int n, istate_t *istate) 68 69 { 69 70 uint64_t intrcv; -
kernel/arch/sparc64/src/trap/trap_table.S
red166f7 r6767c1d 60 60 .global instruction_access_exception 61 61 instruction_access_exception: 62 SIMPLE_HANDLER do_instruction_access_exc62 PREEMPTIBLE_HANDLER do_instruction_access_exc 63 63 64 64 /* TT = 0x10, TL = 0, illegal_instruction */ … … 66 66 .global illegal_instruction 67 67 illegal_instruction: 68 SIMPLE_HANDLER do_illegal_instruction68 PREEMPTIBLE_HANDLER do_illegal_instruction 69 69 70 70 /* TT = 0x24, TL = 0, clean_window handler */ … … 78 78 .global data_access_error 79 79 data_access_error: 80 SIMPLE_HANDLER do_data_access_error80 PREEMPTIBLE_HANDLER do_data_access_error 81 81 82 82 /* TT = 0x34, TL = 0, mem_address_not_aligned */ … … 84 84 .global mem_address_not_aligned 85 85 mem_address_not_aligned: 86 SIMPLE_HANDLER do_mem_address_not_aligned86 PREEMPTIBLE_HANDLER do_mem_address_not_aligned 87 87 88 88 /* TT = 0x41, TL = 0, interrupt_level_1 handler */ … … 238 238 .global instruction_access_exception_high 239 239 instruction_access_exception_high: 240 SIMPLE_HANDLER do_instruction_access_exc240 PREEMPTIBLE_HANDLER do_instruction_access_exc 241 241 242 242 /* TT = 0x10, TL > 0, illegal_instruction */ … … 244 244 .global illegal_instruction_high 245 245 illegal_instruction_high: 246 SIMPLE_HANDLER do_illegal_instruction246 PREEMPTIBLE_HANDLER do_illegal_instruction 247 247 248 248 /* TT = 0x24, TL > 0, clean_window handler */ … … 256 256 .global data_access_error_high 257 257 data_access_error_high: 258 SIMPLE_HANDLER do_data_access_error258 PREEMPTIBLE_HANDLER do_data_access_error 259 259 260 260 /* TT = 0x34, TL > 0, mem_address_not_aligned */ … … 262 262 .global mem_address_not_aligned_high 263 263 mem_address_not_aligned_high: 264 SIMPLE_HANDLER do_mem_address_not_aligned264 PREEMPTIBLE_HANDLER do_mem_address_not_aligned 265 265 266 266 /* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
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