Changeset 68656282 in mainline

Timestamp:

2006-02-24T19:59:57Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

578aebf7

Parents:

b6fba84

Message:

Fixes in sparc64 preliminary TLB miss handler.
Compute and insert identity mapping for kernel on the fly.

Location:

arch/sparc64

Files:

• include/mm/tlb.h (modified) (4 diffs)
• src/mm/tlb.c (modified) (4 diffs)

arch/sparc64/include/mm/tlb.h

@@ -112 +112 @@
                 unsigned asi : 8;       /**< ASI. */
                 unsigned tm : 1;        /**< TLB miss. */
-                unsigned : 3;
-                unsigned ft : 5;        /**< Fault type. */
+                unsigned : 1;
+                unsigned ft : 7;        /**< Fault type. */
                 unsigned e : 1;         /**< Side-effect bit. */
                 unsigned ct : 2;        /**< Context Register selection. */
@@ -119 +119 @@
                 unsigned w : 1;         /**< Write bit. */
                 unsigned ow : 1;        /**< Overwrite bit. */
-                unsigned fv : 1;        /**< Fayult Valid bit. */
+                unsigned fv : 1;        /**< Fault Valid bit. */
         } __attribute__ ((packed));
 };
@@ -262 +262 @@
 }
 
+/** Read IMMU TLB Tag Access Register.
+ *
+ * @return Current value of IMMU TLB Tag Access Register.
+ */
+static inline __u64 itlb_tag_access_read(void)
+{
+        return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
+}
+
 /** Write DMMU TLB Tag Access Register.
  *
@@ -271 +280 @@
         flush();
 }
+
+/** Read DMMU TLB Tag Access Register.
+ *
+ * @return Current value of DMMU TLB Tag Access Register.
+ */
+static inline __u64 dtlb_tag_access_read(void)
+{
+        return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
+}
+
 
 /** Write IMMU TLB Data in Register.

arch/sparc64/src/mm/tlb.c

@@ -32 +32 @@
 #include <arch/mm/page.h>
 #include <arch/mm/mmu.h>
+#include <mm/asid.h>
 #include <print.h>
 #include <arch/types.h>
@@ -75 +76 @@
          * We do identity mapping of 4M-page at 4M.
          */
-        tag.value = 0;
+        tag.value = ASID_KERNEL;
         tag.vpn = pg.vpn;
 
@@ -113 +114 @@
         pg.address = 0xc0000000;
 
-        tag.value = 0;
+        tag.value = ASID_KERNEL;
         tag.vpn = pg.vpn;
 
@@ -142 +143 @@
 void fast_data_access_mmu_miss(void)
 {
-        tlb_sfsr_reg_t status;
-        __address address, tpc;
+        tlb_tag_access_reg_t tag;
+        tlb_data_t data;
+        __address tpc;
         char *tpc_str;
         
-        status.value = dtlb_sfsr_read();
-        address = dtlb_sfar_read();
-        tpc = tpc_read();
-        tpc_str = get_symtab_entry(tpc);
-
-        printf("ASI=%B, Context=%s\n", status.asi, context_encoding[status.ct]);
-        printf("Faulting address: %P\n", dtlb_sfar_read());
-        printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
-        panic("%s\n", __FUNCTION__);
+        tag.value = dtlb_tag_access_read();
+        if (tag.context != ASID_KERNEL || tag.vpn == 0) {
+                tpc = tpc_read();
+                tpc_str = get_symtab_entry(tpc);
+
+                printf("Faulting page: %P, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
+                printf("TPC=%P, (%s)\n", tpc, tpc_str ? tpc_str : "?");
+                panic("%s\n", __FUNCTION__);
+        }
+
+        /*
+         * Identity map piece of faulting kernel address space.
+         */
+        data.value = 0;
+        data.v = true;
+        data.size = PAGESIZE_8K;
+        data.pfn = tag.vpn;
+        data.l = false;
+        data.cp = 1;
+        data.cv = 1;
+        data.p = true;
+        data.w = true;
+        data.g = true;
+
+        dtlb_data_in_write(data.value);
 }