Changes in uspace/drv/bus/pci/pciintel/pci.c [2df6f6fe:690d2e7] in mainline

File:

• uspace/drv/bus/pci/pciintel/pci.c (modified) (5 diffs)

uspace/drv/bus/pci/pciintel/pci.c

@@ -38 +38 @@
 
 #include <assert.h>
+#include <byteorder.h>
 #include <stdio.h>
 #include <errno.h>
@@ -231 +232 @@
         void *addr = bus->conf_data_port + (reg & 3);
         
-        pio_write_32(bus->conf_addr_port, conf_addr);
+        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
         
         switch (len) {
         case 1:
+                /* No endianness change for 1 byte */
                 buf[0] = pio_read_8(addr);
                 break;
         case 2:
-                ((uint16_t *) buf)[0] = pio_read_16(addr);
+                ((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));
                 break;
         case 4:
-                ((uint32_t *) buf)[0] = pio_read_32(addr);
+                ((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));
                 break;
         }
@@ -254 +256 @@
         fibril_mutex_lock(&bus->conf_mutex);
         
-        uint32_t conf_addr;
-        conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
+        const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
         void *addr = bus->conf_data_port + (reg & 3);
         
-        pio_write_32(bus->conf_addr_port, conf_addr);
+        pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
         
         switch (len) {
         case 1:
+                /* No endianness change for 1 byte */
                 pio_write_8(addr, buf[0]);
                 break;
         case 2:
-                pio_write_16(addr, ((uint16_t *) buf)[0]);
+                pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0]));
                 break;
         case 4:
-                pio_write_32(addr, ((uint32_t *) buf)[0]);
+                pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));
                 break;
         }
@@ -650 +652 @@
         got_res = true;
         
+        
+        assert(hw_resources.count > 1);
+        assert(hw_resources.resources[0].type == IO_RANGE);
+        assert(hw_resources.resources[0].res.io_range.size >= 4);
+        
+        assert(hw_resources.resources[1].type == IO_RANGE);
+        assert(hw_resources.resources[1].res.io_range.size >= 4);
+        
         ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
             hw_resources.resources[0].res.io_range.address);
-        
-        assert(hw_resources.count > 0);
-        assert(hw_resources.resources[0].type == IO_RANGE);
-        assert(hw_resources.resources[0].res.io_range.size == 8);
+        ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
+            hw_resources.resources[1].res.io_range.address);
         
         bus->conf_io_addr =
             (uint32_t) hw_resources.resources[0].res.io_range.address;
-        
-        if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
+        bus->conf_io_data =
+            (uint32_t) hw_resources.resources[1].res.io_range.address;
+        
+        if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
             &bus->conf_addr_port)) {
                 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
@@ -666 +676 @@
                 goto fail;
         }
-        bus->conf_data_port = (char *) bus->conf_addr_port + 4;
+        if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
+            &bus->conf_data_port)) {
+                ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
+                rc = EADDRNOTAVAIL;
+                goto fail;
+        }
         
         /* Make the bus device more visible. It has no use yet. */