Changeset 69a93d02 in mainline
- Timestamp:
- 2018-01-11T17:35:02Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 665368c
- Parents:
- 4ed803f1
- git-author:
- Salmelu <salmelu@…> (2018-01-11 17:33:44)
- git-committer:
- Salmelu <salmelu@…> (2018-01-11 17:35:02)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/xhci/isoch.c
r4ed803f1 r69a93d02 293 293 bool fed = false; 294 294 295 while (isoch->hw_enqueue != isoch->enqueue) { 295 /* 296 * There might be a case, where no transfer can't be put on the ring immediately 297 * (for endpoints with interval >= 500ms). In that case, the transfer buffers could fill 298 * and the first condition wouldn't be enough to enter the loop. 299 */ 300 while (isoch->hw_enqueue != isoch->enqueue || isoch->transfers[isoch->hw_enqueue].state == ISOCH_FILLED) { 296 301 xhci_isoch_transfer_t * const it = &isoch->transfers[isoch->hw_enqueue]; 297 302
Note:
See TracChangeset
for help on using the changeset viewer.