Changeset 69bd642 in mainline
- Timestamp:
- 2005-09-01T15:47:50Z (19 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 3c56c94
- Parents:
- 79c1593
- Location:
- arch/ia32/src
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
arch/ia32/src/boot/boot.S
r79c1593 r69bd642 51 51 52 52 lgdt gdtr # initialize Global Descriptor Table register 53 lidt idtr # initialize Interrupt Descriptor Table register54 53 55 54 movl %cr0,%eax … … 74 73 75 74 lgdt gdtr 76 lidt idtr77 75 78 76 meeting_point: -
arch/ia32/src/pm.c
r79c1593 r69bd642 166 166 struct descriptor *gdt_p = (struct descriptor *) PA2KA(gdtr.base); 167 167 168 169 /* 170 * Update addresses in GDT and IDT to their virtual counterparts. 171 */ 172 gdtr.base = KA2PA(gdtr.base); 173 idtr.base = (__address) idt; 174 __asm__ volatile ("lgdt %0\n" : : "m" (gdtr)); 175 __asm__ volatile ("lidt %0\n" : : "m" (idtr)); 176 168 177 /* 169 178 * Each CPU has its private GDT and TSS. … … 198 207 * to its own TSS. We just need to load the TR register. 199 208 */ 200 __asm__ ("ltr %0" : : "r" ((__u16) selector(TSS_DES)));209 __asm__ volatile ("ltr %0" : : "r" ((__u16) selector(TSS_DES))); 201 210 202 211 clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels */ -
arch/ia32/src/smp/ap.S
r79c1593 r69bd642 52 52 53 53 lgdt gdtr # initialize Global Descriptor Table register 54 lidt idtr # initialize Interrupt Descriptor Table register55 54 56 55 movl %cr0,%eax
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