Changeset 6a6ebde in mainline

Timestamp:

2013-01-09T19:36:04Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

467f0c0

Parents:

813b024

Message:

arm32: Add some cp15 register values.

Change MODE_ values to enum
Add hybervisor and monitor modes.
Add security extensions header.

Location:

kernel/arch/arm32

Files:

• include/cp15.h (modified) (2 diffs)
• include/regutils.h (modified) (1 diff)
• include/security_ext.h (added)
• src/fpu_context.c (modified) (1 diff)

kernel/arch/arm32/include/cp15.h

@@ -62 +62 @@
 CONTROL_REG_GEN_READ(REVIDR, c0, 0, c0, 6);
 
+enum {
+        ID_PFR0_THUMBEE_MASK = 0xf << 12,
+        ID_PFR0_THUMBEE = 0x1 << 12,
+        ID_PFR0_JAZELLE_MASK = 0xf << 8,
+        ID_PFR0_JAZELLE = 0x1 << 8,
+        ID_PFR0_JAZELLE_CV_CLEAR = 0x2 << 8,
+        ID_PFR0_THUMB_MASK = 0xf << 4,
+        ID_PFR0_THUMB = 0x1 << 4,
+        ID_PFR0_THUMB2 = 0x3 << 4,
+        ID_PFR0_ARM_MASK = 0xf << 0,
+        ID_PFR0_ARM = 0x1 << 0,
+};
 CONTROL_REG_GEN_READ(ID_PFR0, c0, 0, c1, 0);
+
+enum {
+        ID_PFR1_GEN_TIMER_EXT_MASK = 0xf << 16,
+        ID_PFR1_GEN_TIMER_EXT = 0x1 << 16,
+        ID_PFR1_VIRT_EXT_MASK = 0xf << 12,
+        ID_PFR1_VIRT_EXT = 0x1 << 12,
+        ID_PFR1_M_PROF_MASK = 0xf << 8,
+        ID_PFR1_M_PROF_MODEL = 0x2 << 8,
+        ID_PFR1_SEC_EXT_MASK = 0xf << 4,
+        ID_PFR1_SEC_EXT = 0x1 << 4,
+        ID_PFR1_SEC_EXT_RFR = 0x2 << 4,
+        ID_PFR1_ARMV4_MODEL_MASK = 0xf << 0,
+        ID_PFR1_ARMV4_MODEL = 0x1 << 0,
+};
 CONTROL_REG_GEN_READ(ID_PFR1, c0, 0, c1, 1);
 CONTROL_REG_GEN_READ(ID_DFR0, c0, 0, c1, 2);
@@ -94 +120 @@
 CONTROL_REG_GEN_READ(ACTLR, c1, 0, c0, 1);
 CONTROL_REG_GEN_WRITE(ACTLR, c1, 0, c0, 1);
+
+enum {
+        CPACR_ASEDIS_FLAG = 1 << 31,
+        CPACR_D32DIS_FLAG = 1 << 30,
+        CPACR_TRCDIS_FLAG = 1 << 28,
+#define CPACR_CP_MASK(cp) (0x3 << (cp * 2))
+#define CPACR_CP_NO_ACCESS(cp) (0x0 << (cp * 2))
+#define CPACR_CP_PL1_ACCESS(cp) (0x1 << (cp * 2))
+#define CPACR_CP_FULL_ACCESS(cp) (0x3 << (cp * 2))
+};
 CONTROL_REG_GEN_READ(CPACR, c1, 0, c0, 2);
 CONTROL_REG_GEN_WRITE(CPACR, c1, 0, c0, 2);
 
 /* Implemented as part of Security extensions */
+enum {
+        SCR_SIF_FLAG = 1 << 9,
+        SCR_HCE_FLAG = 1 << 8,
+        SCR_SCD_FLAG = 1 << 7,
+        SCR_nET_FLAG = 1 << 6,
+        SCR_AW_FLAG = 1 << 5,
+        SCR_FW_FLAG = 1 << 4,
+        SCR_EA_FLAG = 1 << 3,
+        SCR_FIQ_FLAG = 1 << 2,
+        SCR_IRQ_FLAG = 1 << 1,
+        SCR_NS_FLAG = 1 << 0,
+};
 CONTROL_REG_GEN_READ(SCR, c1, 0, c1, 0);
 CONTROL_REG_GEN_WRITE(SCR, c1, 0, c1, 0);
 CONTROL_REG_GEN_READ(SDER, c1, 0, c1, 1);
 CONTROL_REG_GEN_WRITE(SDER, c1, 0, c1, 1);
+
+enum {
+        NSACR_NSTRCDIS_FLAG = 1 << 20,
+        NSACR_RFR_FLAG = 1 << 19,
+        NSACR_NSASEDIS = 1 << 15,
+        NSACR_NSD32DIS = 1 << 14,
+#define NSACR_CP_FLAG(cp) (1 << cp)
+};
 CONTROL_REG_GEN_READ(NSACR, c1, 0, c1, 2);
 CONTROL_REG_GEN_WRITE(NSACR, c1, 0, c1, 2);

kernel/arch/arm32/include/regutils.h

@@ -66 +66 @@
 
 /* ARM Processor Operation Modes */
-#define USER_MODE        0x10
-#define FIQ_MODE         0x11
-#define IRQ_MODE         0x12
-#define SUPERVISOR_MODE  0x13
-#define ABORT_MODE       0x17
-#define UNDEFINED_MODE   0x1b
-#define SYSTEM_MODE      0x1f
-
+enum {
+        USER_MODE = 0x10,
+        FIQ_MODE = 0x11,
+        IRQ_MODE = 0x12,
+        SUPERVISOR_MODE = 0x13,
+        MONITOR_MODE = 0x16,
+        ABORT_MODE = 0x17,
+        HYPERVISOR_MODE = 0x1a,
+        UNDEFINED_MODE = 0x1b,
+        SYSTEM_MODE = 0x1f,
+        MODE_MASK = 0x1f,
+};
 /* [CS]PRS manipulation macros */
 #define GEN_STATUS_READ(nm, reg) \

kernel/arch/arm32/src/fpu_context.c

@@ -37 +37 @@
 #include <arch.h>
 #include <arch/types.h>
+#include <arch/security_ext.h>
 #include <cpu.h>