Changeset 6b3ee0c5 in mainline
- Timestamp:
- 2012-04-03T04:14:46Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 712a10b
- Parents:
- 4d02595
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/arm32/src/mm.c
r4d02595 r6b3ee0c5 105 105 /* Behave as a client of domains */ 106 106 "ldr r0, =0x55555555\n" 107 "mcr p15, 0, r0, c3, c0, 0\n" 107 "mcr p15, 0, r0, c3, c0, 0\n" 108 108 109 #ifdef PROCESSOR_armv7 110 /* Clean L2 cache */ 111 "mov r12, #0x1\n" //set up to invalidate L2 112 "smc #0\n" //Call SMI monitor 113 114 /* Read Auxiliary control register */ 115 "mrc p15, 0, r0, c1, c0, 1\n" 116 /* Mask to enable L2 cache */ 117 "ldr r1, =0x00000002\n" 118 "orr r0, r0, r1\n" 119 /* Store Auxiliary control register */ 120 "mrc p15, 0, r0, c1, c0, 1\n" 121 #endif 109 122 /* Current settings */ 110 123 "mrc p15, 0, r0, c1, c0, 0\n" 111 124 125 #ifdef PROCESSOR_armv7 112 126 /* Mask to enable paging, alignment and caching */ 113 127 "ldr r1, =0x00000007\n" 128 #else 129 /* Mask to enable paging */ 130 "ldr r1, =0x00000001\n" 131 #endif 114 132 "orr r0, r0, r1\n" 115 133
Note:
See TracChangeset
for help on using the changeset viewer.