Changeset 6b781c0 in mainline
- Timestamp:
- 2007-06-08T15:02:49Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- c03ee1c
- Parents:
- 3ee8a075
- Files:
-
- 39 added
- 79 edited
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
HelenOS.config
r3ee8a075 r6b781c0 20 20 @ "indy" Sgi Indy 21 21 ! [PLATFORM=mips32] MACHINE (choice) 22 23 # Machine 24 @ "gxemul_testarm" GXEmul testarm 25 ! [PLATFORM=arm32] MACHINE (choice) 22 26 23 27 # Compiler -
boot/arch/arm32/Makefile.inc
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 7 Jakub Jermar2 # Copyright (c) 2006 Martin Decky 3 3 # All rights reserved. 4 4 # … … 27 27 # 28 28 29 # 30 # So far, this is just a placeholder. 31 # 29 build: $(BASE)/image.boot 30 31 $(BASE)/image.boot: depend arch/$(ARCH)/loader/image.boot 32 cp arch/$(ARCH)/loader/image.boot $(BASE)/image.boot 33 34 depend: 35 -rm arch/$(ARCH)/loader/image.boot 36 37 arch/$(ARCH)/loader/image.boot: 38 make -C arch/$(ARCH)/loader COMPILER=$(COMPILER) KERNELDIR=../../../$(KERNELDIR) USPACEDIR=../../../$(USPACEDIR) IMAGE=$(IMAGE) 39 40 clean: 41 make -C arch/$(ARCH)/loader clean COMPILER=$(COMPILER) KERNELDIR=../../../$(KERNELDIR) USPACEDIR=../../../$(USPACEDIR) IMAGE=$(IMAGE) 42 -rm -f $(BASE)/image.boot -
boot/boot.config
r3ee8a075 r6b781c0 50 50 @ "ecoff" Ecoff image (GXEmul) 51 51 ! [ARCH=mips32] IMAGE (choice) 52 -
boot/generic/align.h
r3ee8a075 r6b781c0 27 27 */ 28 28 29 /** @addtogroup generic 30 * @{ 31 */ 32 /** @file 33 */ 34 29 35 #ifndef BOOT_ALIGN_H_ 30 36 #define BOOT_ALIGN_H_ … … 38 44 39 45 #endif 46 47 /** @} 48 */ -
boot/generic/gentypes.h
r3ee8a075 r6b781c0 27 27 */ 28 28 29 /** @addtogroup generic 30 * @{ 31 */ 32 /** @file 33 */ 34 29 35 #ifndef BOOT_GENTYPES_H_ 30 36 #define BOOT_GENTYPES_H_ … … 37 43 38 44 #endif 45 46 /** @} 47 */ -
boot/generic/printf.c
r3ee8a075 r6b781c0 27 27 */ 28 28 29 /** @addtogroup generic 30 * @{ 31 */ 32 /** @file 33 */ 34 29 35 #include "printf.h" 30 36 #include "stdarg.h" … … 242 248 va_end(ap); 243 249 } 250 251 /** @} 252 */ -
boot/generic/printf.h
r3ee8a075 r6b781c0 27 27 */ 28 28 29 /** @addtogroup generic 30 * @{ 31 */ 32 /** @file 33 */ 34 29 35 #ifndef BOOT_PRINTF_H_ 30 36 #define BOOT_PRINTF_H_ … … 41 47 42 48 #endif 49 50 /** @} 51 */ -
boot/generic/stdarg.h
r3ee8a075 r6b781c0 27 27 */ 28 28 29 /** @addtogroup generic 30 * @{ 31 */ 32 /** @file 33 */ 34 29 35 #ifndef STDARG_H__ 30 36 #define STDARG_H__ … … 37 43 38 44 #endif 45 46 /** @} 47 */ -
kernel/arch/amd64/include/mm/page.h
r3ee8a075 r6b781c0 82 82 #define PTL2_ENTRIES_ARCH 512 83 83 #define PTL3_ENTRIES_ARCH 512 84 85 #define PTL0_SIZE_ARCH ONE_FRAME 86 #define PTL1_SIZE_ARCH ONE_FRAME 87 #define PTL2_SIZE_ARCH ONE_FRAME 88 #define PTL3_SIZE_ARCH ONE_FRAME 84 89 85 90 #define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff) -
kernel/arch/arm32/Makefile.inc
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 2005 Martin Decky 3 # Copyright (c) 2007 Jakub Jermar 2 # Copyright (c) 2007 Jakub Jermar, Michal Kebrt 4 3 # All rights reserved. 5 4 # … … 33 32 BFD_NAME = elf32-little 34 33 BFD_ARCH = arm 35 BFD = elf32-little34 BFD = binary 36 35 TARGET = arm-linux-gnu 37 36 TOOLCHAIN_DIR = /usr/local/arm 38 37 39 GCC_CFLAGS += 38 KERNEL_LOAD_ADDRESS = 0x80200000 40 39 41 DEFS += -D__32_BITS__ -DMACHINE=$(MACHINE) 40 ifeq ($(MACHINE), gxemul_testarm) 41 DMACHINE = MACHINE_GXEMUL_TESTARM 42 endif 43 44 GCC_CFLAGS += -fno-zero-initialized-in-bss 45 46 DEFS += -D__32_BITS__ -DKERNEL_LOAD_ADDRESS=$(KERNEL_LOAD_ADDRESS) -D$(DMACHINE) 47 48 # Compile with framebuffer support 49 50 ifeq ($(CONFIG_FB), y) 51 DEFS += -DCONFIG_FB -DFB_INVERT_ENDIAN 52 endif 42 53 43 54 ## Compile with hierarchical page tables support. … … 49 60 ## Compile with support for address space identifiers. 50 61 # 51 52 CONFIG_ASID = y53 CONFIG_ASID_FIFO = y 62 # no HW support for ASIDs 63 #CONFIG_ASID = y 64 #CONFIG_ASID_FIFO = y 54 65 55 66 ## Compile with support with software division and multiplication. … … 59 70 60 71 ARCH_SOURCES = \ 72 arch/$(ARCH)/src/start.S \ 73 arch/$(ARCH)/src/asm.S \ 61 74 arch/$(ARCH)/src/arm32.c \ 62 arch/$(ARCH)/src/start.S \63 75 arch/$(ARCH)/src/context.S \ 64 76 arch/$(ARCH)/src/dummy.S \ 77 arch/$(ARCH)/src/panic.S \ 65 78 arch/$(ARCH)/src/cpu/cpu.c \ 66 79 arch/$(ARCH)/src/ddi/ddi.c \ 80 arch/$(ARCH)/src/interrupt.c \ 81 arch/$(ARCH)/src/debug/print.c \ 82 arch/$(ARCH)/src/console.c \ 83 arch/$(ARCH)/src/exception.c \ 84 arch/$(ARCH)/src/userspace.c \ 67 85 arch/$(ARCH)/src/mm/as.c \ 68 86 arch/$(ARCH)/src/mm/frame.c \ 69 arch/$(ARCH)/src/mm/page.c 70 87 arch/$(ARCH)/src/mm/page.c \ 88 arch/$(ARCH)/src/mm/tlb.c \ 89 arch/$(ARCH)/src/mm/memory_init.c \ 90 arch/$(ARCH)/src/mm/page_fault.c 91 92 ifeq ($(MACHINE), gxemul_testarm) 93 ARCH_SOURCES += arch/$(ARCH)/src/drivers/gxemul.c 94 endif 95 -
kernel/arch/arm32/_link.ld.in
r3ee8a075 r6b781c0 7 7 */ 8 8 9 OUTPUT_ARCH(arm) 9 10 ENTRY(kernel_image_start) 10 11 12 11 13 SECTIONS { 14 . = KERNEL_LOAD_ADDRESS; 12 15 .text : { 13 16 ktext_start = .; … … 23 26 LONG(kdata_end - kdata_start); 24 27 hardcoded_load_address = .; 25 LONG(0); /* TODO */ 28 LONG(KERNEL_LOAD_ADDRESS); 29 *(.bss); /* uninitialized static variables */ 30 *(COMMON); /* global variables */ 31 26 32 *(.rodata*); 27 33 *(.sdata); 28 34 *(.reginfo); 35 symbol_table = .; 29 36 *(symtab.*); 30 37 } 31 _gp = . + 0x8000;32 .lit8 : { *(.lit8) }33 .lit4 : { *(.lit4) }34 38 .sbss : { 35 39 *(.sbss); 36 40 *(.scommon); 37 }38 .bss : {39 *(.bss); /* uninitialized static variables */40 *(COMMON); /* global variables */41 41 } 42 42 … … 49 49 *(.note); 50 50 } 51 51 52 } -
kernel/arch/arm32/include/arch.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Empty. 33 34 */ 34 35 -
kernel/arch/arm32/include/arg.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Empty. 33 34 */ 34 35 -
kernel/arch/arm32/include/asm.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 30 30 * @{ 31 31 */ 32 /** @file 32 /** @file 33 * @brief Declarations of functions implemented in assembly. 33 34 */ 34 35 … … 37 38 38 39 #include <arch/types.h> 40 #include <arch/stack.h> 41 #include <config.h> 42 #include <arch/interrupt.h> 39 43 44 /** No such instruction on ARM to sleep CPU. */ 40 45 static inline void cpu_sleep(void) 41 46 { 42 /* TODO */43 47 } 44 48 45 /** Return base address of current stack 49 /** Return base address of current stack. 46 50 * 47 51 * Return the base address of the current stack. … … 51 55 static inline uintptr_t get_stack_base(void) 52 56 { 53 /* TODO */ 54 return NULL; 57 uintptr_t v; 58 asm volatile ( 59 "and %0, sp, %1\n" 60 : "=r" (v) 61 : "r" (~(STACK_SIZE - 1)) 62 ); 63 return v; 55 64 } 56 65 … … 60 69 uintptr_t entry); 61 70 62 extern ipl_t interrupts_disable(void);63 extern ipl_t interrupts_enable(void);64 extern void interrupts_restore(ipl_t ipl);65 extern ipl_t interrupts_read(void);66 67 71 #endif 68 72 -
kernel/arch/arm32/include/atomic.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Ondrej Palkovsky2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 30 30 * @{ 31 31 */ 32 /** @file 32 /** @file 33 * @brief Atomic operations. 33 34 */ 34 35 … … 36 37 #define KERN_arm32_ATOMIC_H_ 37 38 38 #define atomic_inc(x) ((void) atomic_add(x, 1)) 39 #define atomic_dec(x) ((void) atomic_add(x, -1)) 40 41 #define atomic_postinc(x) (atomic_add(x, 1) - 1) 42 #define atomic_postdec(x) (atomic_add(x, -1) + 1) 43 44 #define atomic_preinc(x) atomic_add(x, 1) 45 #define atomic_predec(x) atomic_add(x, -1) 46 47 /* Atomic addition of immediate value. 39 /** Atomic addition. 48 40 * 49 * @param val Memory location to which will be the immediate value added.50 * @param i Signed immediate that will be added to *val.41 * @param val Where to add. 42 * @param i Value to be added. 51 43 * 52 44 * @return Value after addition. … … 54 46 static inline long atomic_add(atomic_t *val, int i) 55 47 { 56 /* TODO */ 57 return (val->count += i); 48 int ret; 49 volatile long *mem = &(val->count); 50 51 asm volatile ( 52 "1:\n" 53 "ldr r2, [%1] \n" 54 "add r3, r2, %2 \n" 55 "str r3, %0 \n" 56 "swp r3, r3, [%1] \n" 57 "cmp r3, r2 \n" 58 "bne 1b \n" 59 60 : "=m" (ret) 61 : "r" (mem), "r" (i) 62 : "r3", "r2" 63 ); 64 65 return ret; 66 } 67 68 /** Atomic increment. 69 * 70 * @param val Variable to be incremented. 71 */ 72 static inline void atomic_inc(atomic_t *val) 73 { 74 atomic_add(val, 1); 75 } 76 77 /** Atomic decrement. 78 * 79 * @param val Variable to be decremented. 80 */ 81 static inline void atomic_dec(atomic_t *val) { 82 atomic_add(val, -1); 83 } 84 85 /** Atomic pre-increment. 86 * 87 * @param val Variable to be incremented. 88 * @return Value after incrementation. 89 */ 90 static inline long atomic_preinc(atomic_t *val) 91 { 92 return atomic_add(val, 1); 93 } 94 95 /** Atomic pre-decrement. 96 * 97 * @param val Variable to be decremented. 98 * @return Value after decrementation. 99 */ 100 static inline long atomic_predec(atomic_t *val) 101 { 102 return atomic_add(val, -1); 103 } 104 105 /** Atomic post-increment. 106 * 107 * @param val Variable to be incremented. 108 * @return Value before incrementation. 109 */ 110 static inline long atomic_postinc(atomic_t *val) 111 { 112 return atomic_add(val, 1) - 1; 113 } 114 115 /** Atomic post-decrement. 116 * 117 * @param val Variable to be decremented. 118 * @return Value before decrementation. 119 */ 120 static inline long atomic_postdec(atomic_t *val) 121 { 122 return atomic_add(val, -1) + 1; 58 123 } 59 124 -
kernel/arch/arm32/include/barrier.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Memory barriers. 33 34 */ 34 35 -
kernel/arch/arm32/include/byteorder.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Endianness definitions. 33 34 */ 34 35 -
kernel/arch/arm32/include/context.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Thread context. 33 34 */ 34 35 … … 36 37 #define KERN_arm32_CONTEXT_H_ 37 38 38 /* 39 * Put one item onto the stack to support get_stack_base() and align it up. 40 */ 41 #define SP_DELTA 0 /* TODO */ 39 #include <align.h> 40 #include <arch/stack.h> 42 41 42 /* Put one item onto the stack to support get_stack_base() and align it up. */ 43 #define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) 43 44 44 45 #ifndef __ASM__ … … 46 47 #include <arch/types.h> 47 48 48 /* 49 * Only save registers that must be preserved across functioncalls.49 /** Thread context containing registers that must be preserved across function 50 * calls. 50 51 */ 51 52 typedef struct { 53 uint32_t cpu_mode; 52 54 uintptr_t sp; 53 55 uintptr_t pc; 56 57 uint32_t r4; 58 uint32_t r5; 59 uint32_t r6; 60 uint32_t r7; 61 uint32_t r8; 62 uint32_t r9; 63 uint32_t r10; 64 uint32_t r11; 65 54 66 ipl_t ipl; 55 67 } context_t; 68 56 69 57 70 #endif /* __ASM__ */ -
kernel/arch/arm32/include/cpu.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief CPU identification. 33 34 */ 34 35 … … 39 40 #include <arch/asm.h> 40 41 42 43 /** Struct representing ARM CPU identifiaction. */ 41 44 typedef struct { 45 /** Implementator (vendor) number. */ 46 uint32_t imp_num; 47 48 /** Variant number. */ 49 uint32_t variant_num; 50 51 /** Architecture number. */ 52 uint32_t arch_num; 53 54 /** Primary part number. */ 55 uint32_t prim_part_num; 56 57 /** Revision number. */ 58 uint32_t rev_num; 42 59 } cpu_arch_t; 43 60 44 61 #endif 45 62 -
kernel/arch/arm32/include/cycle.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Martin Decky2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Count of CPU cycles. 33 34 */ 34 35 … … 36 37 #define KERN_arm32_CYCLE_H_ 37 38 39 /** Returns count of CPU cycles. 40 * 41 * No such instruction on ARM to get count of cycles. 42 * 43 * @return Count of CPU cycles. 44 */ 38 45 static inline uint64_t get_cycle(void) 39 46 { 40 /* TODO */41 47 return 0; 42 48 } -
kernel/arch/arm32/include/debug.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Empty. 33 34 */ 34 35 -
kernel/arch/arm32/include/elf.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief ARM ELF constants. 33 34 */ 34 35 -
kernel/arch/arm32/include/exception.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 2003-2004 Jakub Jermar 2 * Copyright (c) 2007 Michal Kebrt, Petr Stepan 3 * 3 4 * All rights reserved. 4 5 * … … 31 32 */ 32 33 /** @file 34 * @brief Exception declarations. 33 35 */ 34 36 … … 37 39 38 40 #include <arch/types.h> 41 #include <arch/regutils.h> 39 42 43 /** If defined, forces using of high exception vectors. */ 44 #define HIGH_EXCEPTION_VECTORS 45 46 #ifdef HIGH_EXCEPTION_VECTORS 47 #define EXC_BASE_ADDRESS 0xffff0000 48 #else 49 #define EXC_BASE_ADDRESS 0x0 50 #endif 51 52 /* Exception Vectors */ 53 #define EXC_RESET_VEC (EXC_BASE_ADDRESS + 0x0) 54 #define EXC_UNDEF_INSTR_VEC (EXC_BASE_ADDRESS + 0x4) 55 #define EXC_SWI_VEC (EXC_BASE_ADDRESS + 0x8) 56 #define EXC_PREFETCH_ABORT_VEC (EXC_BASE_ADDRESS + 0xc) 57 #define EXC_DATA_ABORT_VEC (EXC_BASE_ADDRESS + 0x10) 58 #define EXC_IRQ_VEC (EXC_BASE_ADDRESS + 0x18) 59 #define EXC_FIQ_VEC (EXC_BASE_ADDRESS + 0x1c) 60 61 /* Exception numbers */ 62 #define EXC_RESET 0 63 #define EXC_UNDEF_INSTR 1 64 #define EXC_SWI 2 65 #define EXC_PREFETCH_ABORT 3 66 #define EXC_DATA_ABORT 4 67 #define EXC_IRQ 5 68 #define EXC_FIQ 6 69 70 71 /** Kernel stack pointer. 72 * 73 * It is set when thread switches to user mode, 74 * and then used for exception handling. 75 */ 76 extern uintptr_t supervisor_sp; 77 78 79 /** Temporary exception stack pointer. 80 * 81 * Temporary stack is used in exceptions handling routines 82 * before switching to thread's kernel stack. 83 */ 84 extern uintptr_t exc_stack; 85 86 87 /** Struct representing CPU state saved when an exception occurs. */ 40 88 typedef struct { 41 /* TODO */ 89 uint32_t spsr; 90 uint32_t sp; 91 uint32_t lr; 92 93 uint32_t r0; 94 uint32_t r1; 95 uint32_t r2; 96 uint32_t r3; 97 uint32_t r4; 98 uint32_t r5; 99 uint32_t r6; 100 uint32_t r7; 101 uint32_t r8; 102 uint32_t r9; 103 uint32_t r10; 104 uint32_t r11; 105 uint32_t r12; 106 107 uint32_t pc; 42 108 } istate_t; 43 109 110 111 /** Sets Program Counter member of given istate structure. 112 * 113 * @param istate istate structure 114 * @param retaddr new value of istate's PC member 115 */ 44 116 static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) 45 117 { 46 /* TODO */ 118 istate->pc = retaddr; 47 119 } 48 120 49 /** Return true if exception happened while in userspace */ 121 122 /** Returns true if exception happened while in userspace. */ 50 123 static inline int istate_from_uspace(istate_t *istate) 51 124 { 52 /* TODO */ 53 return 0; 125 return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; 54 126 } 127 128 129 /** Returns Program Counter member of given istate structure. */ 55 130 static inline unative_t istate_get_pc(istate_t *istate) 56 131 { 57 /* TODO */ 58 return 0; 132 return istate->pc; 59 133 } 134 135 136 extern void install_exception_handlers(void); 137 extern void exception_init(void); 138 extern void print_istate(istate_t *istate); 139 60 140 61 141 #endif -
kernel/arch/arm32/include/faddr.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Function address conversion. 33 34 */ 34 35 … … 38 39 #include <arch/types.h> 39 40 41 /** Calculate absolute address of function referenced by fptr pointer. 42 * 43 * @param fptr Function pointer. 44 */ 40 45 #define FADDR(fptr) ((uintptr_t) (fptr)) 41 46 -
kernel/arch/arm32/include/fpu_context.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Vana2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief FPU context (not implemented). 34 * 35 * GXemul doesn't support FPU on its ARM CPU. 33 36 */ 34 37 … … 38 41 #include <arch/types.h> 39 42 40 #define FPU_CONTEXT_ALIGN 0 /* TODO */43 #define FPU_CONTEXT_ALIGN 0 41 44 42 45 typedef struct { -
kernel/arch/arm32/include/interrupt.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 28 28 29 29 /** @addtogroup arm32interrupt 30 * @ingroup interrupt31 30 * @{ 32 31 */ 33 32 /** @file 33 * @brief Declarations of interrupt controlling routines. 34 34 */ 35 35 … … 37 37 #define KERN_arm32_INTERRUPT_H_ 38 38 39 #define IVT_ITEMS 0 /* TODO */ 40 #define IVT_FIRST 0 /* TODO */ 39 #include <arch/types.h> 40 41 /** Initial size of exception dispatch table. */ 42 #define IVT_ITEMS 6 43 44 /** Index of the first item in exception dispatch table. */ 45 #define IVT_FIRST 0 46 47 48 extern void interrupt_init(void); 49 extern ipl_t interrupts_disable(void); 50 extern ipl_t interrupts_enable(void); 51 extern void interrupts_restore(ipl_t ipl); 52 extern ipl_t interrupts_read(void); 53 41 54 42 55 #endif -
kernel/arch/arm32/include/memstr.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Memory manipulating functions declarations. 33 34 */ 34 35 -
kernel/arch/arm32/include/mm/as.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Address space manipulating functions declarations. 33 34 */ 34 35 … … 38 39 #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0 39 40 40 #define KERNEL_ADDRESS_SPACE_START_ARCH 41 #define KERNEL_ADDRESS_SPACE_END_ARCH 42 #define USER_ADDRESS_SPACE_START_ARCH 43 #define USER_ADDRESS_SPACE_END_ARCH 41 #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000 42 #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff 43 #define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000 44 #define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff 44 45 45 46 #define USTACK_ADDRESS_ARCH (0x80000000 - PAGE_SIZE) … … 53 54 #define as_destructor_arch(as) (as != as) 54 55 #define as_create_arch(as, flags) (as != as) 56 #define as_install_arch(as) 55 57 #define as_deinstall_arch(as) 56 58 #define as_invalidate_translation_cache(as, page, cnt) -
kernel/arch/arm32/include/mm/asid.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Martin Decky2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief ASIDs related declarations. 34 * 35 * ARM CPUs doesn't support ASIDs. 33 36 */ 34 37 … … 38 41 #include <arch/types.h> 39 42 40 #define ASID_MAX_ARCH 3 /* TODO*/43 #define ASID_MAX_ARCH 3 /* minimal required number */ 41 44 42 45 typedef uint8_t asid_t; 46 47 /* 48 * This works due to fact that this file is never included alone but only 49 * through "generic/include/mm/asid.h" where ASID_START is defined. 50 */ 51 #define asid_get() (ASID_START + 1) 52 53 #define asid_put(asid) 43 54 44 55 #endif -
kernel/arch/arm32/include/mm/frame.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Frame related declarations. 33 34 */ 34 35 … … 36 37 #define KERN_arm32_FRAME_H_ 37 38 38 #define FRAME_WIDTH 0 /* TODO*/39 #define FRAME_WIDTH 12 /* 4KB frames */ 39 40 #define FRAME_SIZE (1 << FRAME_WIDTH) 40 41 … … 42 43 #ifndef __ASM__ 43 44 45 #include <arch/types.h> 46 47 #define BOOT_PAGE_TABLE_SIZE 0x4000 48 #define BOOT_PAGE_TABLE_ADDRESS 0x4000 49 50 #define BOOT_PAGE_TABLE_START_FRAME (BOOT_PAGE_TABLE_ADDRESS >> FRAME_WIDTH) 51 #define BOOT_PAGE_TABLE_SIZE_IN_FRAMES (BOOT_PAGE_TABLE_SIZE >> FRAME_WIDTH) 52 53 extern uintptr_t last_frame; 54 44 55 extern void frame_arch_init(void); 56 extern void boot_page_table_free(void); 45 57 46 58 #endif /* __ASM__ */ -
kernel/arch/arm32/include/mm/memory_init.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Memory information functions declarations. 33 34 */ 34 35 … … 38 39 #include <config.h> 39 40 40 #define get_memory_size() CONFIG_MEMORY_SIZE /* TODO */ 41 size_t get_memory_size(void); 41 42 42 43 #endif -
kernel/arch/arm32/include/mm/page.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2007 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Paging related declarations. 33 34 */ 34 35 … … 37 38 38 39 #include <arch/mm/frame.h> 40 #include <mm/mm.h> 41 #include <arch/exception.h> 39 42 40 43 #define PAGE_WIDTH FRAME_WIDTH … … 53 56 #ifdef KERNEL 54 57 55 #define PTL0_ENTRIES_ARCH 0 /* TODO */ 56 #define PTL1_ENTRIES_ARCH 0 /* TODO */ 57 #define PTL2_ENTRIES_ARCH 0 /* TODO */ 58 #define PTL3_ENTRIES_ARCH 0 /* TODO */ 59 60 #define PTL0_INDEX_ARCH(vaddr) 0 /* TODO */ 61 #define PTL1_INDEX_ARCH(vaddr) 0 /* TODO */ 62 #define PTL2_INDEX_ARCH(vaddr) 0 /* TODO */ 63 #define PTL3_INDEX_ARCH(vaddr) 0 /* TODO */ 64 65 #define SET_PTL0_ADDRESS_ARCH(ptl0) 66 67 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) 0 /* TODO */ 68 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) 0 /* TODO */ 69 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) 0 /* TODO */ 70 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) 0 /* TODO */ 71 72 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) /* TODO */ 73 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) /* TODO */ 74 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) /* TODO */ 75 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) /* TODO */ 76 77 #define GET_PTL1_FLAGS_ARCH(ptl0, i) 0 /* TODO */ 78 #define GET_PTL2_FLAGS_ARCH(ptl1, i) 0 /* TODO */ 79 #define GET_PTL3_FLAGS_ARCH(ptl2, i) 0 /* TODO */ 80 #define GET_FRAME_FLAGS_ARCH(ptl3, i) 0 /* TODO */ 81 82 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) /* TODO */ 83 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) /* TODO */ 84 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) /* TODO */ 85 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) /* TODO */ 86 87 #define PTE_VALID_ARCH(pte) 0 /* TODO */ 88 #define PTE_PRESENT_ARCH(pte) 0 /* TODO */ 89 #define PTE_GET_FRAME_ARCH(pte) 0 /* TODO */ 90 #define PTE_WRITABLE_ARCH(pte) 0 /* TODO */ 91 #define PTE_EXECUTABLE_ARCH(pte) 0 /* TODO */ 58 #define PTL0_ENTRIES_ARCH (2 << 12) /* 4096 */ 59 #define PTL1_ENTRIES_ARCH 0 60 #define PTL2_ENTRIES_ARCH 0 61 62 /* coarse page tables used (256 * 4 = 1KB per page) */ 63 #define PTL3_ENTRIES_ARCH (2 << 8) /* 256 */ 64 65 #define PTL0_SIZE_ARCH FOUR_FRAMES 66 #define PTL1_SIZE_ARCH 0 67 #define PTL2_SIZE_ARCH 0 68 #define PTL3_SIZE_ARCH ONE_FRAME 69 70 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff) 71 #define PTL1_INDEX_ARCH(vaddr) 0 72 #define PTL2_INDEX_ARCH(vaddr) 0 73 #define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff) 74 75 #define GET_PTL1_ADDRESS_ARCH(ptl0, i) \ 76 ((pte_t *) ((((pte_level0_t *)(ptl0))[(i)]).coarse_table_addr << 10)) 77 #define GET_PTL2_ADDRESS_ARCH(ptl1, i) \ 78 (ptl1) 79 #define GET_PTL3_ADDRESS_ARCH(ptl2, i) \ 80 (ptl2) 81 #define GET_FRAME_ADDRESS_ARCH(ptl3, i) \ 82 ((uintptr_t) ((((pte_level1_t *)(ptl3))[(i)]).frame_base_addr << 12)) 83 84 #define SET_PTL0_ADDRESS_ARCH(ptl0) \ 85 (set_ptl0_addr((pte_level0_t *) (ptl0))) 86 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \ 87 (((pte_level0_t *) (ptl0))[(i)].coarse_table_addr = (a) >> 10) 88 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) 89 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) 90 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \ 91 (((pte_level1_t *) (ptl3))[(i)].frame_base_addr = (a) >> 12) 92 93 #define GET_PTL1_FLAGS_ARCH(ptl0, i) \ 94 get_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i)) 95 #define GET_PTL2_FLAGS_ARCH(ptl1, i) \ 96 PAGE_PRESENT 97 #define GET_PTL3_FLAGS_ARCH(ptl2, i) \ 98 PAGE_PRESENT 99 #define GET_FRAME_FLAGS_ARCH(ptl3, i) \ 100 get_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i)) 101 102 #define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \ 103 set_pt_level0_flags((pte_level0_t *) (ptl0), (index_t) (i), (x)) 104 #define SET_PTL2_FLAGS_ARCH(ptl1, i, x) 105 #define SET_PTL3_FLAGS_ARCH(ptl2, i, x) 106 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 107 set_pt_level1_flags((pte_level1_t *) (ptl3), (index_t) (i), (x)) 108 109 #define PTE_VALID_ARCH(pte) \ 110 (*((uint32_t *) (pte)) != 0) 111 #define PTE_PRESENT_ARCH(pte) \ 112 (((pte_level0_t *) (pte))->descriptor_type != 0) 113 114 /* pte should point into ptl3 */ 115 #define PTE_GET_FRAME_ARCH(pte) \ 116 (((pte_level1_t *) (pte))->frame_base_addr << FRAME_WIDTH) 117 118 /* pte should point into ptl3 */ 119 #define PTE_WRITABLE_ARCH(pte) \ 120 (((pte_level1_t *) (pte))->access_permission_0 == \ 121 PTE_AP_USER_RW_KERNEL_RW) 122 123 #define PTE_EXECUTABLE_ARCH(pte) \ 124 1 92 125 93 126 #ifndef __ASM__ 94 127 95 #include <mm/mm.h> 96 #include <arch/exception.h> 97 98 static inline int get_pt_flags(pte_t *pt, index_t i) 99 { 100 return 0; /* TODO */ 101 } 102 103 static inline void set_pt_flags(pte_t *pt, index_t i, int flags) 104 { 105 /* TODO */ 106 return; 107 } 128 /** Level 0 page table entry. */ 129 typedef struct { 130 /* 0b01 for coarse tables, see below for details */ 131 unsigned descriptor_type : 2; 132 unsigned impl_specific : 3; 133 unsigned domain : 4; 134 unsigned should_be_zero : 1; 135 136 /* Pointer to the coarse 2nd level page table (holding entries for small 137 * (4KB) or large (64KB) pages. ARM also supports fine 2nd level page 138 * tables that may hold even tiny pages (1KB) but they are bigger (4KB 139 * per table in comparison with 1KB per the coarse table) 140 */ 141 unsigned coarse_table_addr : 22; 142 } ATTRIBUTE_PACKED pte_level0_t; 143 144 /** Level 1 page table entry (small (4KB) pages used). */ 145 typedef struct { 146 147 /* 0b10 for small pages */ 148 unsigned descriptor_type : 2; 149 unsigned bufferable : 1; 150 unsigned cacheable : 1; 151 152 /* access permissions for each of 4 subparts of a page 153 * (for each 1KB when small pages used */ 154 unsigned access_permission_0 : 2; 155 unsigned access_permission_1 : 2; 156 unsigned access_permission_2 : 2; 157 unsigned access_permission_3 : 2; 158 unsigned frame_base_addr : 20; 159 } ATTRIBUTE_PACKED pte_level1_t; 160 161 162 /* Level 1 page tables access permissions */ 163 164 /** User mode: no access, privileged mode: no access. */ 165 #define PTE_AP_USER_NO_KERNEL_NO 0 166 167 /** User mode: no access, privileged mode: read/write. */ 168 #define PTE_AP_USER_NO_KERNEL_RW 1 169 170 /** User mode: read only, privileged mode: read/write. */ 171 #define PTE_AP_USER_RO_KERNEL_RW 2 172 173 /** User mode: read/write, privileged mode: read/write. */ 174 #define PTE_AP_USER_RW_KERNEL_RW 3 175 176 177 /* pte_level0_t and pte_level1_t descriptor_type flags */ 178 179 /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ 180 #define PTE_DESCRIPTOR_NOT_PRESENT 0 181 182 /** pte_level0_t coarse page table flag (used in descriptor_type). */ 183 #define PTE_DESCRIPTOR_COARSE_TABLE 1 184 185 /** pte_level1_t small page table flag (used in descriptor type). */ 186 #define PTE_DESCRIPTOR_SMALL_PAGE 2 187 188 189 /** Sets the address of level 0 page table. 190 * 191 * @param pt Pointer to the page table to set. 192 */ 193 static inline void set_ptl0_addr( pte_level0_t *pt) 194 { 195 asm volatile ( 196 "mcr p15, 0, %0, c2, c0, 0 \n" 197 : 198 : "r"(pt) 199 ); 200 } 201 202 203 /** Returns level 0 page table entry flags. 204 * 205 * @param pt Level 0 page table. 206 * @param i Index of the entry to return. 207 */ 208 static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i) 209 { 210 pte_level0_t *p = &pt[i]; 211 int np = (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT); 212 213 return (np << PAGE_PRESENT_SHIFT) | (1 << PAGE_USER_SHIFT) | 214 (1 << PAGE_READ_SHIFT) | (1 << PAGE_WRITE_SHIFT) | 215 (1 << PAGE_EXEC_SHIFT) | (1 << PAGE_CACHEABLE_SHIFT); 216 } 217 218 /** Returns level 1 page table entry flags. 219 * 220 * @param pt Level 1 page table. 221 * @param i Index of the entry to return. 222 */ 223 static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i) 224 { 225 pte_level1_t *p = &pt[i]; 226 227 int dt = p->descriptor_type; 228 int ap = p->access_permission_0; 229 230 return ((dt == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) | 231 ((ap == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT) | 232 ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT) | 233 ((ap == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT) | 234 ((ap != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT) | 235 ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_READ_SHIFT) | 236 ((ap == PTE_AP_USER_NO_KERNEL_RW) << PAGE_WRITE_SHIFT) | 237 (1 << PAGE_EXEC_SHIFT) | 238 (p->bufferable << PAGE_CACHEABLE); 239 } 240 241 242 /** Sets flags of level 0 page table entry. 243 * 244 * @param pt level 0 page table 245 * @param i index of the entry to be changed 246 * @param flags new flags 247 */ 248 static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags) 249 { 250 pte_level0_t *p = &pt[i]; 251 252 if (flags & PAGE_NOT_PRESENT) { 253 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; 254 /* 255 * Ensures that the entry will be recognized as valid when 256 * PTE_VALID_ARCH applied. 257 */ 258 p->should_be_zero = 1; 259 } else { 260 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; 261 p->should_be_zero = 0; 262 } 263 } 264 265 266 /** Sets flags of level 1 page table entry. 267 * 268 * We use same access rights for the whole page. When page is not preset we 269 * store 1 in acess_rigts_3 so that at least one bit is 1 (to mark correct 270 * page entry, see #PAGE_VALID_ARCH). 271 * 272 * @param pt Level 1 page table. 273 * @param i Index of the entry to be changed. 274 * @param flags New flags. 275 */ 276 static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags) 277 { 278 pte_level1_t *p = &pt[i]; 279 280 if (flags & PAGE_NOT_PRESENT) { 281 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; 282 p->access_permission_3 = 1; 283 } else { 284 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; 285 p->access_permission_3 = p->access_permission_0; 286 } 287 288 p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; 289 290 /* default access permission */ 291 p->access_permission_0 = p->access_permission_1 = 292 p->access_permission_2 = p->access_permission_3 = 293 PTE_AP_USER_NO_KERNEL_RW; 294 295 if (flags & PAGE_USER) { 296 if (flags & PAGE_READ) { 297 p->access_permission_0 = p->access_permission_1 = 298 p->access_permission_2 = p->access_permission_3 = 299 PTE_AP_USER_RO_KERNEL_RW; 300 } 301 if (flags & PAGE_WRITE) { 302 p->access_permission_0 = p->access_permission_1 = 303 p->access_permission_2 = p->access_permission_3 = 304 PTE_AP_USER_RW_KERNEL_RW; 305 } 306 } 307 } 308 108 309 109 310 extern void page_arch_init(void); 110 311 312 111 313 #endif /* __ASM__ */ 112 314 -
kernel/arch/arm32/include/mm/tlb.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief TLB related declarations. 33 34 */ 34 35 -
kernel/arch/arm32/include/proc/task.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Task related declarations. 33 34 */ 34 35 -
kernel/arch/arm32/include/proc/thread.h
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief Thread related declarations. 33 34 */ 34 35 … … 47 48 /** @} 48 49 */ 49 -
kernel/arch/arm32/include/types.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2007 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Type definitions. 33 34 */ 34 35 35 36 #ifndef KERN_arm32_TYPES_H_ 36 37 #define KERN_arm32_TYPES_H_ 38 39 #ifndef DOXYGEN 40 # define ATTRIBUTE_PACKED __attribute__ ((packed)) 41 #else 42 # define ATTRIBUTE_PACKED 43 #endif 37 44 38 45 #define NULL 0 … … 70 77 typedef int32_t devno_t; 71 78 72 /** Page Table Entry. */ 79 80 /** Page table entry. 81 * 82 * We have different structs for level 0 and level 1 page table entries. 83 * See page.h for definition of pte_level*_t. 84 */ 73 85 typedef struct { 74 /* placeholder */86 unsigned dummy : 32; 75 87 } pte_t; 76 88 -
kernel/arch/arm32/src/arm32.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief ARM32 architecture specific functions. 33 34 */ 34 35 36 #include <arch.h> 37 #include <arch/boot.h> 38 #include <config.h> 39 #include <arch/console.h> 40 #include <ddi/device.h> 41 #include <genarch/fb/fb.h> 42 #include <genarch/fb/visuals.h> 43 #include <ddi/irq.h> 44 #include <arch/debug/print.h> 45 #include <print.h> 46 #include <config.h> 47 #include <interrupt.h> 48 #include <arch/regutils.h> 49 #include <arch/machine.h> 50 #include <userspace.h> 35 51 36 #include <arch.h> 52 /** Information about loaded tasks. */ 53 bootinfo_t bootinfo; 37 54 55 /** Performs arm32 specific initialization before main_bsp() is called. */ 38 56 void arch_pre_main(void) 39 57 { 40 /* TODO */ 58 int i; 59 60 init.cnt = bootinfo.cnt; 61 62 for (i = 0; i < bootinfo.cnt; ++i) { 63 init.tasks[i].addr = bootinfo.tasks[i].addr; 64 init.tasks[i].size = bootinfo.tasks[i].size; 65 } 66 41 67 } 42 68 69 /** Performs arm32 specific initialization before mm is initialized. */ 43 70 void arch_pre_mm_init(void) 44 71 { 45 /* TODO */ 72 /* It is not assumed by default */ 73 interrupts_disable(); 46 74 } 47 75 76 /** Performs arm32 specific initialization afterr mm is initialized. */ 48 77 void arch_post_mm_init(void) 49 78 { 50 /* TODO */ 79 machine_hw_map_init(); 80 81 /* Initialize exception dispatch table */ 82 exception_init(); 83 84 interrupt_init(); 85 86 console_init(device_assign_devno()); 87 88 #ifdef CONFIG_FB 89 fb_init(machine_get_fb_address(), 640, 480, 1920, VISUAL_RGB_8_8_8); 90 #endif 51 91 } 52 92 93 /** Performs arm32 specific tasks needed after cpu is initialized. 94 * 95 * Currently the function is empty. 96 */ 53 97 void arch_post_cpu_init(void) 54 98 { 55 /* TODO */56 99 } 57 100 101 102 /** Performs arm32 specific tasks needed before the multiprocessing is 103 * initialized. 104 * 105 * Currently the function is empty because SMP is not supported. 106 */ 58 107 void arch_pre_smp_init(void) 59 108 { 60 /* TODO */61 109 } 62 110 111 112 /** Performs arm32 specific tasks needed after the multiprocessing is 113 * initialized. 114 * 115 * Currently the function is empty because SMP is not supported. 116 */ 63 117 void arch_post_smp_init(void) 64 118 { 65 /* TODO */66 119 } 67 120 68 /** Perform arm32 specific tasks needed before the new task is run. */ 121 122 /** Performs arm32 specific tasks needed before the new task is run. */ 69 123 void before_task_runs_arch(void) 70 124 { 71 /* TODO */125 tlb_invalidate_all(); 72 126 } 73 127 74 /** Perform arm32 specific tasks needed before the new thread is scheduled. */ 128 129 /** Performs arm32 specific tasks needed before the new thread is scheduled. 130 * 131 * It sets supervisor_sp. 132 */ 75 133 void before_thread_runs_arch(void) 76 134 { 77 /* TODO */ 135 uint8_t *stck; 136 137 stck = &THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]; 138 supervisor_sp = (uintptr_t) stck; 78 139 } 79 140 141 /** Performs arm32 specific tasks before a thread stops running. 142 * 143 * Currently the function is empty. 144 */ 80 145 void after_thread_ran_arch(void) 81 146 { 82 /* TODO */83 147 } 84 148 85 void arch_reboot(void) 149 /** Halts CPU. */ 150 void cpu_halt(void) 86 151 { 87 // TODO 88 while (1); 152 machine_cpu_halt(); 153 } 154 155 /** Reboot. */ 156 void arch_reboot() 157 { 158 /* not implemented */ 159 for (;;) 160 ; 89 161 } 90 162 -
kernel/arch/arm32/src/context.S
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 3-2004 Jakub Jermar2 # Copyright (c) 2007 Petr Stepan 3 3 # All rights reserved. 4 4 # … … 33 33 34 34 context_save_arch: 35 /* TODO */ 35 stmfd sp!, {r1} 36 mrs r1, cpsr 37 and r1, r1, #0x1f 38 stmia r0!, {r1} 39 ldmfd sp!, {r1} 40 41 stmia r0!, {sp, lr} 42 stmia r0!, {r4-r11} 43 44 mov r0, #1 45 mov pc, lr 46 47 48 context_restore_arch: 49 ldmia r0!, {r4} 50 mrs r5, cpsr 51 bic r5, r5, #0x1f 52 orr r5, r5, r4 53 msr cpsr_c, r5 54 55 ldmia r0!, {sp, lr} 56 ldmia r0!, {r4-r11} 36 57 37 context_restore_arch: 38 /* TODO */58 mov r0, #0 59 mov pc, lr -
kernel/arch/arm32/src/cpu/cpu.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief CPU identification. 33 34 */ 34 35 36 #include <arch/cpu.h> 35 37 #include <cpu.h> 38 #include <arch.h> 36 39 #include <print.h> 37 40 41 /** Number of indexes left out in the #imp_data array */ 42 #define IMP_DATA_START_OFFSET 0x40 43 44 /** Implementators (vendor) names */ 45 static char *imp_data[] = { 46 "?", /* IMP_DATA_START_OFFSET */ 47 "ARM Ltd", /* 0x41 */ 48 "", /* 0x42 */ 49 "", /* 0x43 */ 50 "Digital Equipment Corporation", /* 0x44 */ 51 "", "", "", "", "", "", "", "", "", "", /* 0x45 - 0x4e */ 52 "", "", "", "", "", "", "", "", "", "", /* 0x4f - 0x58 */ 53 "", "", "", "", "", "", "", "", "", "", /* 0x59 - 0x62 */ 54 "", "", "", "", "", "", /* 0x63 - 0x68 */ 55 "Intel Corporation" /* 0x69 */ 56 }; 57 58 /** Length of the #imp_data array */ 59 static int imp_data_length = sizeof(imp_data) / sizeof(char *); 60 61 /** Architecture names */ 62 static char *arch_data[] = { 63 "?", /* 0x0 */ 64 "4", /* 0x1 */ 65 "4T", /* 0x2 */ 66 "5", /* 0x3 */ 67 "5T", /* 0x4 */ 68 "5TE", /* 0x5 */ 69 "5TEJ", /* 0x6 */ 70 "6" /* 0x7 */ 71 }; 72 73 /** Length of the #arch_data array */ 74 static int arch_data_length = sizeof(arch_data) / sizeof(char *); 75 76 77 /** Retrieves processor identification from CP15 register 0. 78 * 79 * @param cpu Structure for storing CPU identification. 80 */ 81 static void arch_cpu_identify(cpu_arch_t *cpu) 82 { 83 uint32_t ident; 84 asm volatile ( 85 "mrc p15, 0, %0, c0, c0, 0\n" 86 : "=r" (ident) 87 ); 88 89 cpu->imp_num = ident >> 24; 90 cpu->variant_num = (ident << 8) >> 28; 91 cpu->arch_num = (ident << 12) >> 28; 92 cpu->prim_part_num = (ident << 16) >> 20; 93 cpu->rev_num = (ident << 28) >> 28; 94 } 95 96 /** Does nothing on ARM. */ 38 97 void cpu_arch_init(void) 39 98 { 40 99 } 41 100 42 void cpu_identify(void) 101 /** Retrieves processor identification and stores it to #CPU.arch */ 102 void cpu_identify(void) 43 103 { 44 /* TODO */104 arch_cpu_identify(&CPU->arch); 45 105 } 46 106 107 /** Prints CPU identification. */ 47 108 void cpu_print_report(cpu_t *m) 48 109 { 49 /* TODO */ 110 char * vendor = imp_data[0]; 111 char * architecture = arch_data[0]; 112 cpu_arch_t * cpu_arch = &m->arch; 113 114 if ((cpu_arch->imp_num) > 0 && 115 (cpu_arch->imp_num < (imp_data_length + IMP_DATA_START_OFFSET))) { 116 vendor = imp_data[cpu_arch->imp_num - IMP_DATA_START_OFFSET]; 117 } 118 119 if ((cpu_arch->arch_num) > 0 && 120 (cpu_arch->arch_num < arch_data_length)) { 121 architecture = arch_data[cpu_arch->arch_num]; 122 } 123 124 printf("cpu%d: vendor=%s, architecture=ARM%s, part number=%x, " 125 "variant=%x, revision=%x\n", 126 m->id, vendor, architecture, cpu_arch->prim_part_num, 127 cpu_arch->variant_num, cpu_arch->rev_num); 50 128 } 51 129 -
kernel/arch/arm32/src/ddi/ddi.c
r3ee8a075 r6b781c0 31 31 */ 32 32 /** @file 33 * @brief DDI. 33 34 */ 34 35 -
kernel/arch/arm32/src/dummy.S
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 3-2004 Jakub Jermar2 # Copyright (c) 2007 Michal Kebry, Pavel Jancik, Petr Stepan 3 3 # All rights reserved. 4 4 # … … 31 31 .global calibrate_delay_loop 32 32 .global asm_delay_loop 33 .global dummy 34 .global arch_grab_console 35 .global arch_release_console 36 .global cpu_halt 33 37 34 .global fpu_context_restore 38 35 .global fpu_context_save 39 36 .global fpu_enable 40 37 .global fpu_init 41 .global interrupts_disable 42 .global interrupts_enable 43 .global interrupts_read 44 .global interrupts_restore 45 .global memcpy 46 .global memcpy_from_uspace 47 .global memcpy_to_uspace 48 .global memsetb 49 .global panic_printf 50 .global symbol_table 38 51 39 .global sys_tls_set 52 .global tlb_invalidate_asid 53 .global tlb_invalidate_pages 54 .global userspace 55 40 .global dummy 41 56 42 calibrate_delay_loop: 43 mov pc, lr 44 57 45 asm_delay_loop: 46 mov pc, lr 58 47 59 arch_grab_console:60 arch_release_console:61 cpu_halt:62 48 fpu_context_restore: 49 mov pc, lr 50 63 51 fpu_context_save: 52 mov pc, lr 53 64 54 fpu_enable: 55 mov pc, lr 56 65 57 fpu_init: 66 interrupts_disable: 67 interrupts_enable: 68 interrupts_read: 69 interrupts_restore: 70 memcpy: 71 memcpy_from_uspace: 72 memcpy_to_uspace: 73 memsetb: 74 panic_printf: 75 symbol_table: 58 mov pc, lr 59 60 # not used on ARM 76 61 sys_tls_set: 77 tlb_invalidate_asid:78 tlb_invalidate_pages:79 userspace:80 62 81 63 dummy: 82 83 0: 84 b 0b 64 mov pc, lr -
kernel/arch/arm32/src/mm/as.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Address space functions. 33 34 */ 34 35 … … 39 40 #include <arch.h> 40 41 41 /** Architecture dependent address space init. */ 42 /** Architecture dependent address space init. 43 * 44 * Since ARM supports page tables, #as_pt_operations are used. 45 */ 42 46 void as_arch_init(void) 43 47 { 44 as_operations = &as_pt_operations; 45 asid_fifo_init(); 46 } 47 48 /** Install address space. 49 * 50 * Install ASID. 51 * 52 * @param as Address space structure. 53 */ 54 void as_install_arch(as_t *as) 55 { 56 /* TODO */ 48 as_operations = &as_pt_operations; 57 49 } 58 50 -
kernel/arch/arm32/src/mm/frame.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Frame related functions. 33 34 */ 34 35 35 36 #include <mm/frame.h> 37 #include <arch/mm/frame.h> 38 #include <config.h> 39 #include <arch/debug/print.h> 36 40 37 /** Create memory zones. */ 41 /** Address of the last frame in the memory. */ 42 uintptr_t last_frame = 0; 43 44 /** Creates memory zones. */ 38 45 void frame_arch_init(void) 39 46 { 40 /* TODO */ 47 /* all memory as one zone */ 48 zone_create(0, ADDR2PFN(config.memory_size), 49 BOOT_PAGE_TABLE_START_FRAME + BOOT_PAGE_TABLE_SIZE_IN_FRAMES, 0); 50 last_frame = config.memory_size; 51 52 /* blacklist boot page table */ 53 frame_mark_unavailable(BOOT_PAGE_TABLE_START_FRAME, 54 BOOT_PAGE_TABLE_SIZE_IN_FRAMES); 55 } 56 57 /** Frees the boot page table. */ 58 void boot_page_table_free(void) 59 { 60 int i; 61 for (i = 0; i < BOOT_PAGE_TABLE_SIZE_IN_FRAMES; i++) { 62 frame_free(i * FRAME_SIZE + BOOT_PAGE_TABLE_ADDRESS); 63 } 41 64 } 42 65 -
kernel/arch/arm32/src/mm/page.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 3-2004 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Paging related functions. 33 34 */ 34 35 … … 36 37 #include <genarch/mm/page_pt.h> 37 38 #include <mm/page.h> 39 #include <align.h> 40 #include <config.h> 41 #include <arch/exception.h> 42 #include <typedefs.h> 43 #include <arch/types.h> 44 #include <interrupt.h> 45 #include <arch/mm/frame.h> 38 46 47 /** Initializes page tables. 48 * 49 * 1:1 virtual-physical mapping is created in kernel address space. Mapping 50 * for table with exception vectors is also created. 51 */ 39 52 void page_arch_init(void) 40 53 { 54 uintptr_t cur; 55 int flags; 56 41 57 page_mapping_operations = &pt_mapping_operations; 58 59 flags = PAGE_CACHEABLE; 60 61 /* PA2KA(identity) mapping for all frames until last_frame */ 62 for (cur = 0; cur < last_frame; cur += FRAME_SIZE) { 63 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); 64 } 65 66 /* create mapping for exception table at high offset */ 67 #ifdef HIGH_EXCEPTION_VECTORS 68 void *virtaddr = frame_alloc(ONE_FRAME, FRAME_KA); 69 page_mapping_insert(AS_KERNEL, EXC_BASE_ADDRESS, KA2PA(virtaddr), flags); 70 #else 71 #error "Only high exception vector supported now" 72 #endif 73 74 as_switch(NULL, AS_KERNEL); 75 76 boot_page_table_free(); 42 77 } 43 78 44 /** Map device into kernel space. */ 79 /** Maps device into the kernel space. 80 * 81 * Maps physical address of device into kernel virtual address space (so it can 82 * be accessed only by kernel through virtual address). 83 * 84 * @param physaddr Physical address where device is connected. 85 * @param size Length of area where device is present. 86 * 87 * @return Virtual address where device will be accessible. 88 */ 45 89 uintptr_t hw_map(uintptr_t physaddr, size_t size) 46 90 { 47 /* TODO */ 48 return NULL; 91 if (last_frame + ALIGN_UP(size, PAGE_SIZE) > 92 KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) { 93 panic("Unable to map physical memory %p (%d bytes)", 94 physaddr, size) 95 } 96 97 uintptr_t virtaddr = PA2KA(last_frame); 98 pfn_t i; 99 for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) { 100 page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), 101 physaddr + PFN2ADDR(i), 102 PAGE_NOT_CACHEABLE | PAGE_READ | PAGE_WRITE | PAGE_KERNEL); 103 } 104 105 last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE); 106 return virtaddr; 49 107 } 50 108 -
kernel/arch/arm32/src/start.S
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 3-2007 Jakub Jermar2 # Copyright (c) 2007 Michal Kebrt 3 3 # All rights reserved. 4 4 # … … 27 27 # 28 28 29 #include <arch/asm/boot.h> 30 31 .text 32 29 33 .global kernel_image_start 34 .global exc_stack 35 .global supervisor_sp 36 30 37 kernel_image_start: 38 39 # switch to supervisor mode 40 mrs r3, cpsr 41 bic r3, r3, #0x1f 42 orr r3, r3, #0x13 43 msr cpsr_c, r3 44 45 ldr sp, =temp_stack 31 46 32 /* TODO */ 47 cmp r2, #0 48 beq bootinfo_end 49 50 ldr r3, =bootinfo 51 52 bootinfo_loop: 53 ldr r4, [r1] 54 str r4, [r3] 55 56 add r1, r1, #4 57 add r3, r3, #4 58 add r2, r2, #-4 59 60 cmp r2, #0 61 bne bootinfo_loop 33 62 34 0: 35 b 0b 63 bootinfo_end: 64 65 bl arch_pre_main 66 67 bl main_bsp 68 69 .space TEMP_STACK_SIZE 70 temp_stack: 71 72 .space 1024 73 exc_stack: 74 75 supervisor_sp: 76 .space 4 77 -
kernel/arch/ia32/include/mm/page.h
r3ee8a075 r6b781c0 61 61 #define PTL2_ENTRIES_ARCH 0 62 62 #define PTL3_ENTRIES_ARCH 1024 63 64 #define PTL0_SIZE_ARCH ONE_FRAME 65 #define PTL1_SIZE_ARCH 0 66 #define PTL2_SIZE_ARCH 0 67 #define PTL3_SIZE_ARCH ONE_FRAME 63 68 64 69 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) -
kernel/arch/ia32xen/include/mm/page.h
r3ee8a075 r6b781c0 62 62 #define PTL3_ENTRIES_ARCH 1024 63 63 64 #define PTL0_SIZE_ARCH ONE_FRAME 65 #define PTL1_SIZE_ARCH 0 66 #define PTL2_SIZE_ARCH 0 67 #define PTL3_SIZE_ARCH ONE_FRAME 68 64 69 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) 65 70 #define PTL1_INDEX_ARCH(vaddr) 0 -
kernel/arch/mips32/include/mm/page.h
r3ee8a075 r6b781c0 74 74 #define PTL2_ENTRIES_ARCH 0 75 75 #define PTL3_ENTRIES_ARCH 4096 76 77 #define PTL0_SIZE_ARCH ONE_FRAME 78 #define PTL1_SIZE_ARCH 0 79 #define PTL2_SIZE_ARCH 0 80 #define PTL3_SIZE_ARCH ONE_FRAME 76 81 77 82 #define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26) -
kernel/arch/ppc32/include/mm/page.h
r3ee8a075 r6b781c0 71 71 #define PTL3_ENTRIES_ARCH 1024 72 72 73 #define PTL0_SIZE_ARCH ONE_FRAME 74 #define PTL1_SIZE_ARCH 0 75 #define PTL2_SIZE_ARCH 0 76 #define PTL3_SIZE_ARCH ONE_FRAME 77 73 78 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) 74 79 #define PTL1_INDEX_ARCH(vaddr) 0 -
kernel/arch/ppc64/include/mm/page.h
r3ee8a075 r6b781c0 70 70 #define PTL2_ENTRIES_ARCH 0 71 71 #define PTL3_ENTRIES_ARCH 1024 72 73 #define PTL0_SIZE_ARCH ONE_FRAME 74 #define PTL1_SIZE_ARCH 0 75 #define PTL2_SIZE_ARCH 0 76 #define PTL3_SIZE_ARCH ONE_FRAME 72 77 73 78 #define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff) -
kernel/doc/AUTHORS
r3ee8a075 r6b781c0 1 1 Jakub Jermar <jermar@helenos.eu> 2 Martin Decky <decky@helenos.eu> 2 3 Ondrej Palkovsky <palkovsky@helenos.eu> 3 Martin Decky <decky@helenos.eu>4 4 Jakub Vana <vana@helenos.eu> 5 5 Josef Cejka <cejka@helenos.eu> 6 Michal Kebrt <michalek.k@seznam.cz> 6 7 Sergey Bondari <bondari@helenos.eu> 8 Pavel Jancik <alfik.009@seznam.cz> 9 Petr Stepan <stepan.petr@volny.cz> 7 10 Michal Konopa <mkonopa@seznam.cz> 8 -
kernel/doc/doxygroups.h
r3ee8a075 r6b781c0 28 28 */ 29 29 30 30 31 /** 31 32 * @cond amd64 32 33 * @defgroup amd64proc amd64 34 * @ingroup proc 35 * @endcond 36 */ 37 38 /** 39 * @cond arm32 40 * @defgroup arm32proc arm32 33 41 * @ingroup proc 34 42 * @endcond … … 103 111 * @endcond 104 112 */ 113 114 /** 115 * @cond arm32 116 * @defgroup arm32mm arm32 117 * @ingroup mm 118 * @endcond 119 */ 105 120 106 121 /** … … 172 187 * @endcond 173 188 */ 189 190 /** 191 * @cond arm32 192 * @defgroup arm32ddi arm32 193 * @ingroup ddi 194 * @endcond 195 */ 174 196 175 197 /** … … 229 251 * @endcond 230 252 */ 253 254 /** 255 * @cond arm32 256 * @defgroup arm32debug arm32 257 * @ingroup debug 258 * @endcond 259 */ 231 260 232 261 /** … … 286 315 * @endcond 287 316 */ 317 318 /** 319 * @cond arm32 320 * @defgroup arm32interrupt arm32 321 * @ingroup interrupt 322 * @endcond 323 */ 288 324 289 325 /** … … 347 383 * @endcond 348 384 */ 385 386 /** 387 * @cond arm32 388 * @defgroup arm32 arm32 389 * @ingroup others 390 * @endcond 391 */ 349 392 350 393 /** -
kernel/genarch/include/mm/page_pt.h
r3ee8a075 r6b781c0 55 55 #define PTL2_ENTRIES PTL2_ENTRIES_ARCH 56 56 #define PTL3_ENTRIES PTL3_ENTRIES_ARCH 57 58 /* Table sizes in each level */ 59 #define PTL0_SIZE PTL0_SIZE_ARCH 60 #define PTL1_SIZE PTL1_SIZE_ARCH 61 #define PTL2_SIZE PTL2_SIZE_ARCH 62 #define PTL3_SIZE PTL3_SIZE_ARCH 57 63 58 64 /* -
kernel/genarch/src/mm/as_pt.c
r3ee8a075 r6b781c0 98 98 pte_t *src_ptl0, *dst_ptl0; 99 99 ipl_t ipl; 100 int table_size; 100 101 101 dst_ptl0 = (pte_t *) frame_alloc(ONE_FRAME, FRAME_KA); 102 dst_ptl0 = (pte_t *) frame_alloc(PTL0_SIZE, FRAME_KA); 103 table_size = FRAME_SIZE << PTL0_SIZE; 102 104 103 105 if (flags & FLAG_AS_KERNEL) { 104 memsetb((uintptr_t) dst_ptl0, PAGE_SIZE, 0);106 memsetb((uintptr_t) dst_ptl0, table_size, 0); 105 107 } else { 106 108 uintptr_t src, dst; … … 117 119 dst = (uintptr_t) &dst_ptl0[PTL0_INDEX(KERNEL_ADDRESS_SPACE_START)]; 118 120 119 memsetb((uintptr_t) dst_ptl0, PAGE_SIZE, 0);120 memcpy((void *) dst, (void *) src, PAGE_SIZE- (src - (uintptr_t) src_ptl0));121 memsetb((uintptr_t) dst_ptl0, table_size, 0); 122 memcpy((void *) dst, (void *) src, table_size - (src - (uintptr_t) src_ptl0)); 121 123 mutex_unlock(&AS_KERNEL->lock); 122 124 interrupts_restore(ipl); -
kernel/genarch/src/mm/page_pt.c
r3ee8a075 r6b781c0 76 76 77 77 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT) { 78 newpt = (pte_t *)frame_alloc( ONE_FRAME, FRAME_KA);79 memsetb((uintptr_t)newpt, PAGE_SIZE, 0);78 newpt = (pte_t *)frame_alloc(PTL1_SIZE, FRAME_KA); 79 memsetb((uintptr_t)newpt, FRAME_SIZE << PTL1_SIZE, 0); 80 80 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt)); 81 81 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); … … 85 85 86 86 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT) { 87 newpt = (pte_t *)frame_alloc( ONE_FRAME, FRAME_KA);88 memsetb((uintptr_t)newpt, PAGE_SIZE, 0);87 newpt = (pte_t *)frame_alloc(PTL2_SIZE, FRAME_KA); 88 memsetb((uintptr_t)newpt, FRAME_SIZE << PTL2_SIZE, 0); 89 89 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt)); 90 90 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); … … 94 94 95 95 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT) { 96 newpt = (pte_t *)frame_alloc( ONE_FRAME, FRAME_KA);97 memsetb((uintptr_t)newpt, PAGE_SIZE, 0);96 newpt = (pte_t *)frame_alloc(PTL3_SIZE, FRAME_KA); 97 memsetb((uintptr_t)newpt, FRAME_SIZE << PTL3_SIZE, 0); 98 98 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt)); 99 99 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page), PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | PAGE_WRITE); -
kernel/generic/include/mm/frame.h
r3ee8a075 r6b781c0 46 46 #define ONE_FRAME 0 47 47 #define TWO_FRAMES 1 48 #define FOUR_FRAMES 2 49 48 50 49 51 #ifdef ARCH_STACK_FRAMES -
kernel/generic/src/printf/printf.c
r3ee8a075 r6b781c0 34 34 35 35 #include <print.h> 36 int printf(const char *fmt, ...); 36 37 37 38 int printf(const char *fmt, ...) -
kernel/kernel.config
r3ee8a075 r6b781c0 50 50 51 51 # Machine type 52 @ "gxemul" GXEmul53 ! [ARCH=arm32] MACHINE (choice)54 55 # Machine type56 52 @ "msim" MSIM Simulator 57 53 @ "simics" Virtutech Simics simulator … … 62 58 63 59 # Machine type 60 @ "gxemul_testarm" GXEmul testarm 61 ! [ARCH=arm32] MACHINE (choice) 62 63 # Machine type 64 64 @ "ski" Ski ia64 simulator 65 65 @ "i460GX" i460GX chipset machine … … 67 67 68 68 # Framebuffer support 69 ! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64) ] CONFIG_FB (y/n)69 ! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)|(ARCH=arm32&MACHINE=gxemul_testarm)] CONFIG_FB (y/n) 70 70 71 71 # Framebuffer width -
uspace/kbd/Makefile
r3ee8a075 r6b781c0 33 33 SOFTINT_PREFIX = ../softint 34 34 include $(LIBC_PREFIX)/Makefile.toolchain 35 include ../../Makefile.config 35 36 36 37 CFLAGS += -Iinclude -I../libadt/include … … 71 72 genarch/src/kbd.c 72 73 endif 74 ifeq ($(ARCH), arm32) 75 ifeq ($(MACHINE), gxemul_testarm) 76 ARCH_SOURCES += \ 77 arch/$(ARCH)/src/kbd_gxemul.c 78 endif 79 endif 73 80 74 81 -
uspace/kbd/arch/arm32/include/kbd.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Josef Cejka2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup kbdarm32 arm32 30 * @brief HelenOS arm32 arch dependent parts of uspace keyboard handler. 31 * @ingroup kbd 29 /** @addtogroup kbdarm32 32 30 * @{ 33 31 */ 34 32 /** @file 33 * @brief Empty. 35 34 */ 36 35 -
uspace/kbd/arch/arm32/src/kbd.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Martin Decky2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 33 33 */ 34 34 /** @file 35 * @brief Empty, required by generic Makefile. 35 36 */ 36 37 37 #include <arch/kbd.h>38 #include <ipc/ipc.h>39 #include <sysinfo.h>40 #include <kbd.h>41 #include <keys.h>42 43 int kbd_arch_init(void)44 {45 return 0;46 }47 48 49 int kbd_arch_process(keybuffer_t *keybuffer, ipc_call_t *call)50 {51 return 1;52 }53 38 54 39 /** @} -
uspace/libc/arch/arm32/Makefile.inc
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 5 Martin Decky2 # Copyright (c) 2007 Michal Kebrt, Pavel Jancik 3 3 # All rights reserved. 4 4 # … … 32 32 TARGET = arm-linux-gnu 33 33 TOOLCHAIN_DIR = /usr/local/arm/bin 34 CFLAGS += 34 CFLAGS += -ffixed-r9 -mtp=soft 35 35 LFLAGS += -N ../softint/libsoftint.a 36 36 AFLAGS += … … 39 39 arch/$(ARCH)/src/psthread.S \ 40 40 arch/$(ARCH)/src/thread.c \ 41 arch/$(ARCH)/src/ dummy.S41 arch/$(ARCH)/src/eabi.S 42 42 43 43 BFD_NAME = elf32-little -
uspace/libc/arch/arm32/_link.ld.in
r3ee8a075 r6b781c0 8 8 9 9 SECTIONS { 10 . = 0x 2000;10 . = 0x1000; 11 11 12 .init ALIGN(0x 2000): SUBALIGN(0x2000) {12 .init ALIGN(0x1000): SUBALIGN(0x1000) { 13 13 *(.init); 14 14 } : text 15 15 .text : { 16 16 *(.text); 17 17 *(.rodata*); 18 18 } :text 19 20 .got ALIGN(0x2000) : SUBALIGN(0x2000) { 21 _gp = .; 22 *(.got*); 23 } :data 24 .data : { 19 20 .data ALIGN(0x1000) : SUBALIGN(0x1000) { 25 21 *(.opd); 26 22 *(.data .data.*); 27 23 *(.sdata); 28 24 } :data 25 29 26 .tdata : { 30 27 _tdata_start = .; … … 32 29 _tdata_end = .; 33 30 } :data 31 34 32 .tbss : { 35 33 _tbss_start = .; … … 37 35 _tbss_end = .; 38 36 } :data 37 39 38 .bss : { 40 39 *(.sbss); 41 40 *(.scommon); 42 43 41 *(COMMON); 42 *(.bss); 44 43 } :data 45 46 . = ALIGN(0x 2000);44 45 . = ALIGN(0x1000); 47 46 _heap = .; 48 47 49 48 /DISCARD/ : { 50 49 *(*); 51 } 50 } 51 52 52 } -
uspace/libc/arch/arm32/include/atomic.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Atomic operations. 33 34 */ 34 35 … … 38 39 /** Atomic addition. 39 40 * 40 * @param val Atomic value.41 * @param i mm Value to add.41 * @param val Where to add. 42 * @param i Value to be added. 42 43 * 43 44 * @return Value after addition. 44 45 */ 45 static inline long atomic_add(atomic_t *val, int i mm)46 static inline long atomic_add(atomic_t *val, int i) 46 47 { 47 /* TODO */ 48 return (val->count += imm); 48 int ret; 49 volatile long * mem = &(val->count); 50 51 asm volatile ( 52 "1: \n" 53 "ldr r2, [%1] \n" 54 "add r3, r2, %2 \n" 55 "str r3, %0 \n" 56 "swp r3, r3, [%1] \n" 57 "cmp r3, r2 \n" 58 "bne 1b \n" 59 60 : "=m" (ret) 61 : "r" (mem), "r" (i) 62 : "r3", "r2" 63 ); 64 65 return ret; 49 66 } 50 67 68 69 /** Atomic increment. 70 * 71 * @param val Variable to be incremented. 72 */ 51 73 static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } 74 75 76 /** Atomic decrement. 77 * 78 * @param val Variable to be decremented. 79 */ 52 80 static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } 53 81 54 static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; }55 static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; }56 82 57 static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1); } 58 static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1); } 83 /** Atomic pre-increment. 84 * 85 * @param val Variable to be incremented. 86 * @return Value after incrementation. 87 */ 88 static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); } 89 90 91 /** Atomic pre-decrement. 92 * 93 * @param val Variable to be decremented. 94 * @return Value after decrementation. 95 */ 96 static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); } 97 98 99 /** Atomic post-increment. 100 * 101 * @param val Variable to be incremented. 102 * @return Value before incrementation. 103 */ 104 static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; } 105 106 107 /** Atomic post-decrement. 108 * 109 * @param val Variable to be decremented. 110 * @return Value before decrementation. 111 */ 112 static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1) + 1; } 113 59 114 60 115 #endif -
uspace/libc/arch/arm32/include/config.h
r3ee8a075 r6b781c0 30 30 * @{ 31 31 */ 32 /** @file 32 /** @file 33 * @brief Configuration constants. 33 34 */ 34 35 -
uspace/libc/arch/arm32/include/endian.h
r3ee8a075 r6b781c0 30 30 * @{ 31 31 */ 32 /** @file 32 /** @file 33 * @brief Endianness definition. 33 34 */ 34 35 -
uspace/libc/arch/arm32/include/faddr.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Jakub Jermar2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 30 30 * @{ 31 31 */ 32 /** @file 32 /** @file 33 * @brief Function address conversion. 33 34 */ 34 35 … … 38 39 #include <libarch/types.h> 39 40 40 /** 41 * 42 * Calculate absolute address of function 43 * referenced by fptr pointer. 41 /** Calculate absolute address of function referenced by fptr pointer. 44 42 * 45 43 * @param f Function pointer. 46 *47 44 */ 48 45 #define FADDR(f) (f) -
uspace/libc/arch/arm32/include/limits.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Josef Cejka2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 30 30 * @{ 31 31 */ 32 /** @file 33 * @ingroup libcarm3232 /** @file 33 * @brief Limits declarations. 34 34 */ 35 35 … … 37 37 #define LIBC_arm32__LIMITS_H_ 38 38 39 # 40 # 41 # 42 # 39 #define LONG_MIN MIN_INT32 40 #define LONG_MAX MAX_INT32 41 #define ULONG_MIN MIN_UINT32 42 #define ULONG_MAX MAX_UINT32 43 43 44 44 #endif -
uspace/libc/arch/arm32/include/psthread.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Ondrej Palkovsky2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 30 30 * @{ 31 31 */ 32 /** @file 33 * @ingroup libcarm3232 /** @file 33 * @brief psthread related declarations. 34 34 */ 35 35 … … 38 38 39 39 #include <types.h> 40 #include <align.h> 41 #include "thread.h" 40 42 41 #define SP_DELTA 0 /* TODO */ 43 /** Size of a stack item */ 44 #define STACK_ITEM_SIZE 4 42 45 46 /** Stack alignment - see <a href="http://www.arm.com/support/faqdev/14269.html">ABI</a> for details */ 47 #define STACK_ALIGNMENT 8 48 49 #define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)) 50 51 52 /** Sets data to the context. 53 * 54 * @param c Context (#context_t). 55 * @param _pc Program counter. 56 * @param stack Stack address. 57 * @param size Stack size. 58 * @param ptls Pointer to the TCB. 59 */ 60 #define context_set(c, _pc, stack, size, ptls) \ 61 (c)->pc = (sysarg_t) (_pc); \ 62 (c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; \ 63 (c)->tls = ((sysarg_t)(ptls)) + sizeof(tcb_t) + ARM_TP_OFFSET; 64 65 66 /** Thread context. 67 * 68 * Only registers preserved accross function calls are included. r9 is used 69 * to store a TLS address. -ffixed-r9 gcc forces gcc not to use this 70 * register. -mtp=soft forces gcc to use #__aeabi_read_tp to obtain 71 * TLS address. 72 */ 43 73 typedef struct { 44 74 uint32_t sp; 45 75 uint32_t pc; 76 uint32_t r4; 77 uint32_t r5; 78 uint32_t r6; 79 uint32_t r7; 80 uint32_t r8; 46 81 uint32_t tls; 82 uint32_t r10; 83 uint32_t r11; 47 84 } context_t; 85 48 86 49 87 #endif -
uspace/libc/arch/arm32/include/stackarg.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Josef Cejka2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @brief Empty. 33 34 */ 34 35 -
uspace/libc/arch/arm32/include/syscall.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Martin Decky2 * Copyright (c) 2007 Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup libc 29 /** @addtogroup libcarm32 30 30 * @{ 31 31 */ 32 /** 33 * @file32 /** @file 33 * @brief Empty. 34 34 */ 35 35 -
uspace/libc/arch/arm32/include/thread.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup libc ia6429 /** @addtogroup libcarm32 30 30 * @{ 31 31 */ 32 32 /** @file 33 * @brief Uspace threads and TLS. 33 34 */ 34 35 … … 38 39 #include <unistd.h> 39 40 41 /** Stack initial size. */ 40 42 #define THREAD_INITIAL_STACK_PAGES_NO 1 41 43 44 /** Offsets for accessing __thread variables are shifted 8 bytes higher. */ 45 #define ARM_TP_OFFSET (-8) 46 47 /** TCB (Thread Control Block) struct. 48 * 49 * TLS starts just after this struct. 50 */ 42 51 typedef struct { 52 /** psthread data. */ 43 53 void *pst_data; 44 /* TODO */45 54 } tcb_t; 46 55 56 57 /** Sets TLS address to the r9 register. 58 * 59 * @param tcb TCB (TLS starts behind) 60 */ 47 61 static inline void __tcb_set(tcb_t *tcb) 48 62 { 49 /* TODO */ 63 void *tls = (void *)tcb; 64 tls += sizeof(tcb_t) + ARM_TP_OFFSET; 65 asm volatile ( 66 "mov r9, %0" 67 : 68 : "r"(tls) 69 ); 50 70 } 51 71 72 73 /** Returns TCB address. 74 * 75 * @return TCB address (starts before TLS which address is stored in r9 register). 76 */ 52 77 static inline tcb_t *__tcb_get(void) 53 78 { 54 /* TODO */ 55 return NULL; 79 void *ret; 80 asm volatile ( 81 "mov %0, r9" 82 : "=r"(ret) 83 ); 84 return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t)); 56 85 } 86 87 88 /** Returns TLS address stored. 89 * 90 * Implemented in assembly. 91 * 92 * @return TLS address stored in r9 register 93 */ 94 extern uintptr_t __aeabi_read_tp(void); 57 95 58 96 #endif -
uspace/libc/arch/arm32/include/types.h
r3ee8a075 r6b781c0 30 30 * @{ 31 31 */ 32 /** @file 33 * @ingroup libcarm3232 /** @file 33 * @brief Definitions of basic types like #uintptr_t. 34 34 */ 35 35 -
uspace/libc/arch/arm32/src/eabi.S
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 2007 Jakub Jermar2 # Copyright (c) 2007 Pavel Jancik 3 3 # All rights reserved. 4 4 # … … 30 30 31 31 .global __aeabi_read_tp 32 32 33 __aeabi_read_tp: 33 34 0: 35 b 0b 34 mov r0, r9 35 mov pc, lr -
uspace/libc/arch/arm32/src/entry.s
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 6 Jakub Jermar2 # Copyright (c) 2007 Michal Kebrt, Pavel Jancik 3 3 # All rights reserved. 4 4 # … … 29 29 .section .init, "ax" 30 30 31 .org 0 32 31 33 .global __entry 32 34 .global __entry_driver … … 36 38 # 37 39 __entry: 40 bl __main 41 bl __io_init 42 bl main 43 bl __exit 38 44 39 # 40 # TODO 41 # 45 __entry_driver: 46 bl __main 47 bl main 48 bl __exit 49 -
uspace/libc/arch/arm32/src/psthread.S
r3ee8a075 r6b781c0 1 1 # 2 # Copyright (c) 200 5 Jakub Jermar2 # Copyright (c) 2007 Michal Kebrt 3 3 # All rights reserved. 4 4 # … … 33 33 34 34 context_save: 35 /* TODO */ 35 stmia r0!, {sp, lr} 36 stmia r0!, {r4-r11} 37 38 # return 1 39 mov r0, #1 40 mov pc, lr 36 41 37 42 context_restore: 38 /* TODO */ 43 ldmia r0!, {sp, lr} 44 ldmia r0!, {r4-r11} 45 46 #return 0 47 mov r0, #0 48 mov pc, lr 49 -
uspace/libc/arch/arm32/src/syscall.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 5 Martin Decky2 * Copyright (c) 2007 Pavel Jancik 3 3 * All rights reserved. 4 4 * … … 31 31 */ 32 32 /** @file 33 * @ingroup libcarm3233 * @brief Syscall routine. 34 34 */ 35 35 36 36 #include <libc.h> 37 37 38 39 /** Syscall routine. 40 * 41 * Stores p1-p4, id to r0-r4 registers and calls <code>swi</code> 42 * instruction. Returned value is read from r0 register. 43 * 44 * @param p1 Parameter 1. 45 * @param p2 Parameter 2. 46 * @param p3 Parameter 3. 47 * @param p4 Parameter 4. 48 * @param id Number of syscall. 49 * 50 * @return Syscall return value. 51 */ 38 52 sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3, 39 53 const sysarg_t p4, const syscall_t id) 40 54 { 41 /* TODO */ 42 return 0; 55 register sysarg_t __arm_reg_r0 asm("r0") = p1; 56 register sysarg_t __arm_reg_r1 asm("r1") = p2; 57 register sysarg_t __arm_reg_r2 asm("r2") = p3; 58 register sysarg_t __arm_reg_r3 asm("r3") = p4; 59 register sysarg_t __arm_reg_r4 asm("r4") = id; 60 61 asm volatile ( "swi" 62 : "=r" (__arm_reg_r0) 63 : "r" (__arm_reg_r0), 64 "r" (__arm_reg_r1), 65 "r" (__arm_reg_r2), 66 "r" (__arm_reg_r3), 67 "r" (__arm_reg_r4) 68 ); 69 70 return __arm_reg_r0; 43 71 } 44 72 -
uspace/libc/arch/arm32/src/thread.c
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Ondrej Palkovsky2 * Copyright (c) 2007 Pavel Jancik 3 3 * All rights reserved. 4 4 * … … 33 33 */ 34 34 /** @file 35 * @brief Uspace threads and TLS. 35 36 */ 36 37 … … 38 39 #include <malloc.h> 39 40 40 /** Allocate TLS & TCB for initial module threads41 /** Allocates TLS & TCB. 41 42 * 42 * @param data Start of data section 43 * @return pointer to tcb_t structure 43 * @param data Start of data section (output parameter). 44 * @param size Size of (tbss + tdata) sections. 45 * @return Pointer to the allocated #tcb_t structure. 44 46 */ 45 47 tcb_t * __alloc_tls(void **data, size_t size) 46 48 { 47 /* TODO */ 48 return NULL; 49 tcb_t *result; 50 51 result = malloc(sizeof(tcb_t) + size); 52 *data = ((void *)result) + sizeof(tcb_t); 53 return result; 49 54 } 50 55 56 /** Deallocates TLS & TCB. 57 * 58 * @param tcb TCB structure to be deallocated (along with corresponding TLS). 59 * @param size Not used. 60 */ 51 61 void __free_tls_arch(tcb_t *tcb, size_t size) 52 62 { 53 /* TODO */63 free(tcb); 54 64 } 55 65 -
uspace/libc/arch/arm32/src/thread_entry.s
r3ee8a075 r6b781c0 35 35 # 36 36 __thread_entry: 37 38 # 39 # TODO 40 # 37 b __thread_main -
uspace/softfloat/arch/arm32/include/functions.h
r3ee8a075 r6b781c0 29 29 /** @addtogroup softfloatarm32 arm32 30 30 * @ingroup sfl 31 * @brief softfloat architecture dependent definitions31 * @brief Softfloat architecture dependent definitions. 32 32 * @{ 33 33 */ 34 /** @file 34 /** @file 35 * @brief Softfloat architecture dependent definitions. 35 36 */ 36 37
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