Changeset 6b781c0 in mainline for uspace/libc/arch/arm32/include/thread.h
- Timestamp:
- 2007-06-08T15:02:49Z (18 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- c03ee1c
- Parents:
- 3ee8a075
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
uspace/libc/arch/arm32/include/thread.h
r3ee8a075 r6b781c0 1 1 /* 2 * Copyright (c) 200 6 Jakub Jermar2 * Copyright (c) 2007 Pavel Jancik, Michal Kebrt 3 3 * All rights reserved. 4 4 * … … 27 27 */ 28 28 29 /** @addtogroup libc ia6429 /** @addtogroup libcarm32 30 30 * @{ 31 31 */ 32 32 /** @file 33 * @brief Uspace threads and TLS. 33 34 */ 34 35 … … 38 39 #include <unistd.h> 39 40 41 /** Stack initial size. */ 40 42 #define THREAD_INITIAL_STACK_PAGES_NO 1 41 43 44 /** Offsets for accessing __thread variables are shifted 8 bytes higher. */ 45 #define ARM_TP_OFFSET (-8) 46 47 /** TCB (Thread Control Block) struct. 48 * 49 * TLS starts just after this struct. 50 */ 42 51 typedef struct { 52 /** psthread data. */ 43 53 void *pst_data; 44 /* TODO */45 54 } tcb_t; 46 55 56 57 /** Sets TLS address to the r9 register. 58 * 59 * @param tcb TCB (TLS starts behind) 60 */ 47 61 static inline void __tcb_set(tcb_t *tcb) 48 62 { 49 /* TODO */ 63 void *tls = (void *)tcb; 64 tls += sizeof(tcb_t) + ARM_TP_OFFSET; 65 asm volatile ( 66 "mov r9, %0" 67 : 68 : "r"(tls) 69 ); 50 70 } 51 71 72 73 /** Returns TCB address. 74 * 75 * @return TCB address (starts before TLS which address is stored in r9 register). 76 */ 52 77 static inline tcb_t *__tcb_get(void) 53 78 { 54 /* TODO */ 55 return NULL; 79 void *ret; 80 asm volatile ( 81 "mov %0, r9" 82 : "=r"(ret) 83 ); 84 return (tcb_t *)(ret - ARM_TP_OFFSET - sizeof(tcb_t)); 56 85 } 86 87 88 /** Returns TLS address stored. 89 * 90 * Implemented in assembly. 91 * 92 * @return TLS address stored in r9 register 93 */ 94 extern uintptr_t __aeabi_read_tp(void); 57 95 58 96 #endif
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