Changeset 6ff23ff in mainline
- Timestamp:
- 2018-05-17T13:46:56Z (7 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4f8772d4
- Parents:
- 7c3fb9b
- git-author:
- Jiri Svoboda <jiri@…> (2018-05-16 18:44:36)
- git-committer:
- Jiri Svoboda <jiri@…> (2018-05-17 13:46:56)
- Files:
-
- 18 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/generic/src/printf_core.c
r7c3fb9b r6ff23ff 657 657 658 658 switch (uc) { 659 /*660 * String and character conversions.661 */659 /* 660 * String and character conversions. 661 */ 662 662 case 's': 663 663 retval = print_str(va_arg(ap, char *), width, precision, flags, ps); … … 683 683 continue; 684 684 685 /*686 * Integer values687 */685 /* 686 * Integer values 687 */ 688 688 case 'P': 689 689 /* Pointer */ … … 715 715 break; 716 716 717 /* Percentile itself */717 /* Percentile itself */ 718 718 case '%': 719 719 j = i; 720 720 continue; 721 721 722 /*723 * Bad formatting.724 */722 /* 723 * Bad formatting. 724 */ 725 725 default: 726 726 /* -
kernel/arch/arm32/include/arch/barrier.h
r7c3fb9b r6ff23ff 49 49 50 50 #if defined PROCESSOR_ARCH_armv7_a 51 /* ARMv7 uses instructions for memory barriers see ARM Architecture reference 51 /* 52 * ARMv7 uses instructions for memory barriers see ARM Architecture reference 52 53 * manual for details: 53 54 * DMB: ch. A8.8.43 page A8-376 … … 69 70 * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4 70 71 */ 71 /* ARMv6- use system control coprocessor (CP15) for memory barrier instructions. 72 /* 73 * ARMv6- use system control coprocessor (CP15) for memory barrier instructions. 72 74 * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs, 73 75 * CP15 implementation is mandatory only for armv6+. … … 86 88 #endif 87 89 #else 88 /* Older manuals mention syscalls as a way to implement cache coherency and 90 /* 91 * Older manuals mention syscalls as a way to implement cache coherency and 89 92 * barriers. See for example ARM Architecture Reference Manual Version D 90 93 * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28) … … 123 126 inst_barrier(); /* Wait for Inst refetch */\ 124 127 } while (0) 125 /* @note: Cache type register is not available in uspace. We would need 126 * to export the cache line value, or use syscall for uspace smc_coherence */ 128 /* 129 * @note: Cache type register is not available in uspace. We would need 130 * to export the cache line value, or use syscall for uspace smc_coherence 131 */ 127 132 #define smc_coherence_block(a, l) \ 128 133 do { \ -
kernel/arch/arm32/src/fpu_context.c
r7c3fb9b r6ff23ff 117 117 static int fpu_have_coprocessor_access(void) 118 118 { 119 /*120 * The register containing the information (CPACR) is not available on armv6- 121 * rely on user decision to use CONFIG_FPU.122 */119 /* 120 * The register containing the information (CPACR) is not available 121 * on armv6-. Rely on user decision to use CONFIG_FPU. 122 */ 123 123 #ifdef PROCESSOR_ARCH_armv7_a 124 124 const uint32_t cpacr = CPACR_read(); 125 /* FPU needs access to coprocessor 10 and 11. 126 * Moreover they need to have same access enabled */ 125 /* 126 * FPU needs access to coprocessor 10 and 11. 127 * Moreover, they need to have same access enabled 128 */ 127 129 if (((cpacr & CPACR_CP_MASK(10)) != CPACR_CP_FULL_ACCESS(10)) && 128 130 ((cpacr & CPACR_CP_MASK(11)) != CPACR_CP_FULL_ACCESS(11))) { … … 131 133 } 132 134 #endif 135 133 136 return 1; 134 137 } … … 147 150 static void fpu_enable_coprocessor_access(void) 148 151 { 149 /*150 * The register containing the information (CPACR) is not available on armv6- 151 * rely on user decision to use CONFIG_FPU.152 */152 /* 153 * The register containing the information (CPACR) is not available 154 * on armv6-. Rely on user decision to use CONFIG_FPU. 155 */ 153 156 #ifdef PROCESSOR_ARCH_armv7_a 154 157 /* Allow coprocessor access */ 155 158 uint32_t cpacr = CPACR_read(); 156 /* FPU needs access to coprocessor 10 and 11. 157 * Moreover, they need to have same access enabled */ 159 /* 160 * FPU needs access to coprocessor 10 and 11. 161 * Moreover, they need to have same access enabled 162 */ 158 163 cpacr &= ~(CPACR_CP_MASK(10) | CPACR_CP_MASK(11)); 159 164 cpacr |= (CPACR_CP_FULL_ACCESS(10) | CPACR_CP_FULL_ACCESS(11)); … … 172 177 fpexc_write(0); 173 178 fpu_enable(); 174 /* Mask all exception traps, 179 /* 180 * Mask all exception traps, 175 181 * The bits are RAZ/WI on archs that don't support fpu exc traps. 176 182 */ -
kernel/generic/src/ipc/sysipc.c
r7c3fb9b r6ff23ff 119 119 120 120 121 /* **********************************************************************121 /* 122 122 * Functions that preprocess answer before sending it to the recepient. 123 * **********************************************************************/123 */ 124 124 125 125 /** Decide if the caller (e.g. ipc_answer()) should save the old call contents … … 228 228 } 229 229 230 /* ******************************************************************************230 /* 231 231 * Functions called to process received call/answer before passing it to uspace. 232 * ******************************************************************************/232 */ 233 233 234 234 /** Do basic kernel processing of received call answer. -
kernel/generic/src/printf/printf_core.c
r7c3fb9b r6ff23ff 784 784 785 785 switch (uc) { 786 /*787 * String and character conversions.788 */786 /* 787 * String and character conversions. 788 */ 789 789 case 's': 790 790 if (qualifier == PrintfQualifierLong) … … 816 816 continue; 817 817 818 /*819 * Integer values820 */818 /* 819 * Integer values 820 */ 821 821 case 'P': 822 822 /* Pointer */ … … 848 848 break; 849 849 850 /* Percentile itself */851 850 case '%': 851 /* Percentile itself */ 852 852 j = i; 853 853 continue; 854 854 855 /*856 * Bad formatting.857 */855 /* 856 * Bad formatting. 857 */ 858 858 default: 859 859 /* -
kernel/generic/src/udebug/udebug_ipc.c
r7c3fb9b r6ff23ff 54 54 { 55 55 switch (IPC_GET_ARG1(call->data)) { 56 /* future UDEBUG_M_REGS_WRITE, UDEBUG_M_MEM_WRITE: */56 /* future UDEBUG_M_REGS_WRITE, UDEBUG_M_MEM_WRITE: */ 57 57 default: 58 58 break; … … 193 193 194 194 IPC_SET_RETVAL(call->data, 0); 195 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 196 same code in process_answer() can be used 197 (no way to distinguish method in answer) */ 195 /* 196 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 197 * same code in process_answer() can be used 198 * (no way to distinguish method in answer) 199 */ 198 200 IPC_SET_ARG1(call->data, uspace_addr); 199 201 IPC_SET_ARG2(call->data, copied); … … 238 240 239 241 IPC_SET_RETVAL(call->data, 0); 240 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 241 same code in process_answer() can be used 242 (no way to distinguish method in answer) */ 242 /* 243 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 244 * same code in process_answer() can be used 245 * (no way to distinguish method in answer) 246 */ 243 247 IPC_SET_ARG1(call->data, uspace_addr); 244 248 IPC_SET_ARG2(call->data, to_copy); … … 285 289 286 290 IPC_SET_RETVAL(call->data, 0); 287 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 288 same code in process_answer() can be used 289 (no way to distinguish method in answer) */ 291 /* 292 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 293 * same code in process_answer() can be used 294 * (no way to distinguish method in answer) 295 */ 290 296 IPC_SET_ARG1(call->data, uspace_addr); 291 297 IPC_SET_ARG2(call->data, to_copy); … … 326 332 327 333 IPC_SET_RETVAL(call->data, 0); 328 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 329 same code in process_answer() can be used 330 (no way to distinguish method in answer) */ 334 /* 335 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 336 * same code in process_answer() can be used 337 * (no way to distinguish method in answer) 338 */ 331 339 IPC_SET_ARG1(call->data, uspace_addr); 332 340 IPC_SET_ARG2(call->data, 6 * sizeof(sysarg_t)); … … 367 375 368 376 IPC_SET_RETVAL(call->data, 0); 369 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 370 same code in process_answer() can be used 371 (no way to distinguish method in answer) */ 377 /* 378 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 379 * same code in process_answer() can be used 380 * (no way to distinguish method in answer) 381 */ 372 382 IPC_SET_ARG1(call->data, uspace_addr); 373 383 IPC_SET_ARG2(call->data, to_copy); … … 406 416 407 417 IPC_SET_RETVAL(call->data, 0); 408 /* ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 409 same code in process_answer() can be used 410 (no way to distinguish method in answer) */ 418 /* 419 * ARG1=dest, ARG2=size as in IPC_M_DATA_READ so that 420 * same code in process_answer() can be used 421 * (no way to distinguish method in answer) 422 */ 411 423 IPC_SET_ARG1(call->data, uspace_dst); 412 424 IPC_SET_ARG2(call->data, size); -
uspace/app/trace/trace.c
r7c3fb9b r6ff23ff 723 723 o = oper_new("vfs_mount", 2, arg_def, V_ERRNO, 0, resp_def); 724 724 proto_add_oper(p, VFS_IN_MOUNT, o); 725 /* o = oper_new("unmount", 0, arg_def); 726 proto_add_oper(p, VFS_IN_UNMOUNT, o);*/ 725 #if 0 726 o = oper_new("unmount", 0, arg_def); 727 proto_add_oper(p, VFS_IN_UNMOUNT, o); 728 #endif 727 729 o = oper_new("vfs_sync", 1, arg_def, V_ERRNO, 0, resp_def); 728 730 proto_add_oper(p, VFS_IN_SYNC, o); -
uspace/app/websrv/websrv.c
r7c3fb9b r6ff23ff 375 375 verbose = true; 376 376 break; 377 /* Long options with double dash */378 377 case '-': 378 /* Long options with double dash */ 379 379 if (str_lcmp(argv[*index] + 2, "help", 5) == 0) { 380 380 usage(); -
uspace/drv/hid/atkbd/atkbd.c
r7c3fb9b r6ff23ff 309 309 async_answer_0(icall_handle, ENOTSUP); 310 310 break; 311 /*312 * This might be ugly but async_callback_receive_start makes no313 * difference for incorrect call and malloc failure.314 */315 311 case IPC_M_CONNECT_TO_ME: 312 /* 313 * This might be ugly but async_callback_receive_start makes no 314 * difference for incorrect call and malloc failure. 315 */ 316 316 sess = async_callback_receive_start(EXCHANGE_SERIALIZE, icall); 317 317 -
uspace/drv/hid/ps2mouse/ps2mouse.c
r7c3fb9b r6ff23ff 324 324 325 325 /* Buttons */ 326 /* NOTE: Parsing 4th and 5th button works even if this extension 326 /* 327 * NOTE: Parsing 4th and 5th button works even if this extension 327 328 * is not supported and whole 4th byte should be interpreted 328 329 * as Z-axis movement. the upper 4 bits are just a sign … … 330 331 * (i.e no change since that is the default) and - sign fails 331 332 * the "imb" condition. Thus 4th and 5th buttons are never 332 * down on wheel only extension. */ 333 * down on wheel only extension. 334 */ 333 335 const bool imb = (packet[3] & INTELLIMOUSE_ALWAYS_ZERO) == 0; 334 336 const bool status[] = { … … 411 413 412 414 switch (method) { 413 /* This might be ugly but async_callback_receive_start makes no414 * difference for incorrect call and malloc failure. */415 415 case IPC_M_CONNECT_TO_ME: 416 /* 417 * This might be ugly but async_callback_receive_start makes no 418 * difference for incorrect call and malloc failure. 419 */ 416 420 sess = async_callback_receive_start(EXCHANGE_SERIALIZE, icall); 417 421 /* Probably ENOMEM error, try again. */ -
uspace/drv/hid/xtkbd/xtkbd.c
r7c3fb9b r6ff23ff 364 364 async_answer_0(icall_handle, rc); 365 365 break; 366 /*367 * This might be ugly but async_callback_receive_start makes no368 * difference for incorrect call and malloc failure.369 */370 366 case IPC_M_CONNECT_TO_ME: 367 /* 368 * This might be ugly but async_callback_receive_start makes no 369 * difference for incorrect call and malloc failure. 370 */ 371 371 sess = async_callback_receive_start(EXCHANGE_SERIALIZE, icall); 372 372 -
uspace/lib/c/arch/mips32/src/syscall.c
r7c3fb9b r6ff23ff 31 31 */ 32 32 /** @file 33 33 * @ingroup libcmips32 34 34 */ 35 35 … … 57 57 "r" (__mips_reg_t1), 58 58 "r" (__mips_reg_v0) 59 60 61 62 59 /* 60 * We are a function call, although C 61 * does not know it. 62 */ 63 63 : "%ra" 64 64 ); -
uspace/lib/c/generic/io/printf_core.c
r7c3fb9b r6ff23ff 1499 1499 1500 1500 switch (uc) { 1501 /*1502 * String and character conversions.1503 */1501 /* 1502 * String and character conversions. 1503 */ 1504 1504 case 's': 1505 1505 precision = max(0, precision); … … 1533 1533 continue; 1534 1534 1535 /*1536 * Floating point values1537 */1535 /* 1536 * Floating point values 1537 */ 1538 1538 case 'G': 1539 1539 case 'g': … … 1554 1554 continue; 1555 1555 1556 /*1557 * Integer values1558 */1556 /* 1557 * Integer values 1558 */ 1559 1559 case 'P': 1560 1560 /* Pointer */ … … 1586 1586 break; 1587 1587 1588 /* Percentile itself */1589 1588 case '%': 1589 /* Percentile itself */ 1590 1590 j = i; 1591 1591 continue; 1592 1592 1593 /*1594 * Bad formatting.1595 */1593 /* 1594 * Bad formatting. 1595 */ 1596 1596 default: 1597 1597 /* -
uspace/lib/posix/src/internal/common.h
r7c3fb9b r6ff23ff 53 53 #define _HIDE_LIBC_SYMBOL(symbol) 54 54 55 /* Checks if the value is a failing error code. 55 /** Checks if the value is a failing error code. 56 * 56 57 * If so, writes the error code to errno and returns true. 57 58 */ -
uspace/lib/usb/src/port.c
r7c3fb9b r6ff23ff 224 224 break; 225 225 226 /* We first have to stop the fibril in progress. */227 226 case PORT_CONNECTING: 227 /* We first have to stop the fibril in progress. */ 228 228 port->state = PORT_ERROR; 229 229 fibril_condvar_broadcast(&port->enabled_cv); -
uspace/lib/usbhid/include/usb/hid/usages/kbdgen.h
r7c3fb9b r6ff23ff 32 32 /** @file 33 33 * @brief USB HID key codes. 34 * @details34 * 35 35 * This is not a typical header as by default it is equal to empty file. 36 36 * However, by cleverly defining the USB_HIDUT_KBD_KEY you can use it … … 39 39 * For example, this creates enum for known keys: 40 40 * @code 41 #define USB_HIDUT_KBD_KEY(name, usage_id, l, lc, l1, l2) \ 42 USB_KBD_KEY_##name = usage_id, 43 typedef enum { 44 #include <usb/hidutkbd.h> 45 } usb_key_code_t; 46 @endcode 41 * #define USB_HIDUT_KBD_KEY(name, usage_id, l, lc, l1, l2) \ 42 * USB_KBD_KEY_##name = usage_id, 43 * 44 * typedef enum { 45 * #include <usb/hidutkbd.h> 46 * } usb_key_code_t; 47 * @endcode 47 48 * 48 49 * Maybe, it might be better that you would place such enums into separate -
uspace/lib/usbhid/src/hidpath.c
r7c3fb9b r6ff23ff 213 213 214 214 switch (flags) { 215 /* Path is somewhere in report_path */216 215 case USB_HID_PATH_COMPARE_ANYWHERE: 216 /* 217 * Path is somewhere in report_path 218 */ 217 219 if (path->depth != 1) { 218 220 return 1; … … 239 241 240 242 return 1; 241 break; 242 243 /* The paths must be identical */ 243 244 244 case USB_HID_PATH_COMPARE_STRICT: 245 /* 246 * The paths must be identical 247 */ 245 248 if (report_path->depth != path->depth) { 246 249 return 1; … … 248 251 /* Fallthrough */ 249 252 250 /* Path is prefix of the report_path */251 253 case USB_HID_PATH_COMPARE_BEGIN: 254 /* 255 * Path is prefix of the report_path 256 */ 252 257 report_link = report_path->items.head.next; 253 258 path_link = path->items.head.next; … … 283 288 break; 284 289 285 /* Path is suffix of report_path */286 290 case USB_HID_PATH_COMPARE_END: 291 /* 292 * Path is suffix of report_path 293 */ 287 294 report_link = report_path->items.head.prev; 288 295 path_link = path->items.head.prev; -
uspace/srv/fs/udf/udf_volume.c
r7c3fb9b r6ff23ff 655 655 656 656 switch (FLE16(vol->common.tag.id)) { 657 /* One sector size descriptors */ 657 /* 658 * One sector size descriptors 659 */ 660 658 661 case UDF_TAG_PVD: 659 662 log_msg(LOG_DEFAULT, LVL_DEBUG, "Volume: Primary volume descriptor found"); … … 728 731 break; 729 732 730 /* Relative size descriptors */ 733 /* 734 * Relative size descriptors 735 */ 736 731 737 case UDF_TAG_LVD: 732 738 log_msg(LOG_DEFAULT, LVL_DEBUG, "Volume: Logical volume descriptor found");
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