Changes in uspace/drv/block/ahci/ahci_hw.h [eb3683a:730dce77] in mainline
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uspace/drv/block/ahci/ahci_hw.h (modified) (20 diffs)
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uspace/drv/block/ahci/ahci_hw.h
reb3683a r730dce77 35 35 36 36 #include <sys/types.h> 37 38 /*----------------------------------------------------------------------------*/39 /*-- AHCI standard constants -------------------------------------------------*/40 /*----------------------------------------------------------------------------*/41 42 /** AHCI standard 1.3 - maximum ports. */43 #define AHCI_MAX_PORTS 3244 37 45 38 /*----------------------------------------------------------------------------*/ … … 205 198 typedef union { 206 199 struct { 207 /** Header layout. */200 /** Header layout. */ 208 201 unsigned int hl : 7; 209 /** Multi function device flag. */202 /** Multi function device. */ 210 203 unsigned int mfd : 1; 211 204 }; … … 288 281 typedef struct 289 282 { 290 /** Indicates the minimum grant time that the device291 * wishes grant asserted.283 /** Indicates the minimum grant time (in ? microseconds) 284 * that the device wishes grant asserted. 292 285 */ 293 286 uint8_t u8; … … 304 297 /*-- AHCI Memory Registers ---------------------------------------------------*/ 305 298 /*----------------------------------------------------------------------------*/ 306 307 /** Number of pages for ahci memory registers. */308 #define AHCI_MEMREGS_PAGES_COUNT 8309 299 310 300 /** AHCI Memory register Generic Host Control - HBA Capabilities. */ … … 381 371 382 372 /** AHCI Memory register Interrupt pending register. */ 383 typedef uint32_t ahci_ghc_is_t; 384 385 /** AHCI GHC register offset. */ 386 #define AHCI_GHC_IS_REGISTER_OFFSET 2 387 388 /** AHCI ports registers offset. */ 389 #define AHCI_PORTS_REGISTERS_OFFSET 64 390 391 /** AHCI port registers size. */ 392 #define AHCI_PORT_REGISTERS_SIZE 32 393 394 /** AHCI port IS register offset. */ 395 #define AHCI_PORT_IS_REGISTER_OFFSET 4 373 typedef struct { 374 /** Interrupt pending status, if set, indicates that 375 * the corresponding port has an interrupt pending. 376 */ 377 uint32_t u32; 378 } ahci_ghc_is_t; 396 379 397 380 /** AHCI Memory register Ports implemented. */ … … 444 427 /** Size of the transmit message buffer area in dwords. */ 445 428 uint16_t sz; 446 /* 447 * Offset of the transmit message buffer area in dwords 429 /* Offset of the transmit message buffer area in dwords 448 430 * from the beginning of ABAR 449 431 */ … … 480 462 /** Activity LED hardware driven. */ 481 463 unsigned int alhd : 1; 482 /** Port multiplier support. */464 /** port multiplier support. */ 483 465 unsigned int pm : 1; 484 466 /** Reserved. */ … … 527 509 typedef struct 528 510 { 529 /** Host Capabilities */511 /** Host Capabilities. */ 530 512 uint32_t cap; 531 /** Global Host Control */513 /** Global Host Control. */ 532 514 uint32_t ghc; 533 /** Interrupt Status */534 ahci_ghc_is_t is;535 /** Ports Implemented */515 /** Interrupt Status. */ 516 uint32_t is; 517 /** Ports Implemented. */ 536 518 uint32_t pi; 537 /** Version */519 /** Version. */ 538 520 uint32_t vs; 539 /** Command Completion Coalescing Control */521 /** Command Completion Coalescing Control. */ 540 522 uint32_t ccc_ctl; 541 /** Command Completion Coal escing Ports*/523 /** Command Completion Coalsecing Ports. */ 542 524 uint32_t ccc_ports; 543 /** Enclosure Management Location */525 /** Enclosure Management Location. */ 544 526 uint32_t em_loc; 545 /** Enclosure Management Control */527 /** Enclosure Management Control. */ 546 528 uint32_t em_ctl; 547 /** Host Capabilities Extended */529 /** Host Capabilities Extended. */ 548 530 uint32_t cap2; 549 /** BIOS/OS Handoff Control and Status */531 /** BIOS/OS Handoff Control and Status. */ 550 532 uint32_t bohc; 551 533 } ahci_ghc_t; … … 604 586 605 587 /** AHCI Memory register Port x Interrupt Status. */ 606 typedef uint32_t ahci_port_is_t; 588 typedef union { 589 struct { 590 /** Device to Host Register FIS Interrupt. */ 591 unsigned int dhrs : 1; 592 /** PIO Setup FIS Interrupt. */ 593 unsigned int pss : 1; 594 /** DMA Setup FIS Interrupt. */ 595 unsigned int dss : 1; 596 /** Set Device Bits Interrupt. */ 597 unsigned int sdbs : 1; 598 /** Unknown FIS Interrupt. */ 599 unsigned int ufs : 1; 600 /** Descriptor Processed. */ 601 unsigned int dps : 1; 602 /** Port Connect Change Status. */ 603 unsigned int pcs : 1; 604 /** Device Mechanical Presence Status. */ 605 unsigned int dmps : 1; 606 /** Reserved. */ 607 unsigned int reserved1 : 14; 608 /** PhyRdy Change Status. */ 609 unsigned int prcs : 1; 610 /** Incorrect Port Multiplier Status. */ 611 unsigned int ipms : 1; 612 /** Overflow Status. */ 613 unsigned int ofs : 1; 614 /** Reserved. */ 615 unsigned int reserved2 : 1; 616 /** Interface Non-fatal Error Status. */ 617 unsigned int infs : 1; 618 /** Interface Fatal Error Status. */ 619 unsigned int ifs : 1; 620 /** Host Bus Data Error Status. */ 621 unsigned int hbds : 1; 622 /** Host Bus Fatal Error Status. */ 623 unsigned int hbfs : 1; 624 /** Task File Error Status. */ 625 unsigned int tfes : 1; 626 /** Cold Port Detect Status. */ 627 unsigned int cpds : 1; 628 }; 629 uint32_t u32; 630 } ahci_port_is_t; 607 631 608 632 #define AHCI_PORT_IS_DHRS (1 << 0) … … 659 683 static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is) 660 684 { 661 return port_is & AHCI_PORT_END_OF_OPERATION;685 return port_is.u32 & AHCI_PORT_END_OF_OPERATION; 662 686 } 663 687 … … 671 695 static inline int ahci_port_is_error(ahci_port_is_t port_is) 672 696 { 673 return port_is & AHCI_PORT_IS_ERROR;697 return port_is.u32 & AHCI_PORT_IS_ERROR; 674 698 } 675 699 … … 683 707 static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is) 684 708 { 685 return port_is & AHCI_PORT_IS_PERMANENT_ERROR;709 return port_is.u32 & AHCI_PORT_IS_PERMANENT_ERROR; 686 710 } 687 711 … … 695 719 static inline int ahci_port_is_tfes(ahci_port_is_t port_is) 696 720 { 697 return port_is & AHCI_PORT_IS_TFES;721 return port_is.u32 & AHCI_PORT_IS_TFES; 698 722 } 699 723 … … 793 817 * Values: 794 818 * 7h - fh Reserved, 795 * 6h Slumber - This shall cause the HBA to request a transition 796 * of theinterface to the Slumber state,819 * 6h Slumber - This shall cause the HBA to request a transition of the 820 * interface to the Slumber state, 797 821 * 3h - 5h Reserved, 798 * 2h Partial - This shall cause the HBA to request a transition 799 * of theinterface to the Partial state,822 * 2h Partial - This shall cause the HBA to request a transition of the 823 * interface to the Partial state, 800 824 * 1h Active, 801 825 * 0h No-Op / Idle. … … 832 856 /** LBA Mid Register */ 833 857 uint8_t lba_mr; 834 /** LBA High Register */858 /** LBA High Register */ 835 859 uint8_t lba_hr; 836 860 }; … … 852 876 uint32_t u32; 853 877 } ahci_port_ssts_t; 854 855 /** Device detection active status. */856 #define AHCI_PORT_SSTS_DET_ACTIVE 3857 878 858 879 /** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */ … … 953 974 uint32_t pxfbu; 954 975 /** Port x Interrupt Status. */ 955 ahci_port_is_t pxis;976 uint32_t pxis; 956 977 /** Port x Interrupt Enable. */ 957 978 uint32_t pxie; … … 989 1010 ahci_ghc_t ghc; 990 1011 /** Reserved. */ 991 uint 32_t reserved[13];1012 uint8_t reserved[52]; 992 1013 /** Reserved for NVMHCI. */ 993 uint 32_t reservedfornvmhci[16];1014 uint8_t reservedfornvmhci[64]; 994 1015 /** Vendor Specific registers. */ 995 uint 32_t vendorspecificsregs[24];1016 uint8_t vendorspecificsregs[96]; 996 1017 /** Ports. */ 997 ahci_port_t ports[ AHCI_MAX_PORTS];1018 ahci_port_t ports[32]; 998 1019 } ahci_memregs_t; 999 1020 1000 /** AHCI Command header entry. 1001 * 1002 * This structure is not an AHCI register. 1003 * 1004 */ 1021 /** AHCI Command header entry. */ 1005 1022 typedef volatile struct { 1006 1023 /** Flags. */ … … 1016 1033 } ahci_cmdhdr_t; 1017 1034 1018 /** Clear Busy upon R_OK (C) flag. */ 1019 #define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400 1020 1021 /** Write operation flag. */ 1022 #define AHCI_CMDHDR_FLAGS_WRITE 0x0040 1023 1024 /** 2 DW length command flag. */ 1025 #define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002 1026 1027 /** 5 DW length command flag. */ 1028 #define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005 1029 1030 /** AHCI Command Physical Region Descriptor entry. 1031 * 1032 * This structure is not an AHCI register. 1033 * 1034 */ 1035 /** AHCI Command Physical Region Descriptor entry. */ 1035 1036 typedef volatile struct { 1036 1037 /** Word aligned 32-bit data base address. */ … … 1044 1045 /** Reserved */ 1045 1046 unsigned int reserved2 : 9; 1046 /** Set Interrupt on each operation completion */1047 /** Interrupt on completion */ 1047 1048 unsigned int ioc : 1; 1048 1049 } ahci_cmd_prdt_t;
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