Changeset 7328ff4 in mainline for kernel/arch/sparc64/src/smc.c

Timestamp:

2018-09-06T18:18:52Z (6 years ago)

Author:

Jiří Zárevúcky <jiri.zarevucky@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

ffa73c6

Parents:

d51cca8

git-author:

Jiří Zárevúcky <jiri.zarevucky@…> (2018-08-13 01:29:17)

git-committer:

Jiří Zárevúcky <jiri.zarevucky@…> (2018-09-06 18:18:52)

Message:

Use builtin memory fences for kernel barriers, and convert smp_coherence() into a regular function

File:

• kernel/arch/sparc64/src/smc.c (moved) (moved from kernel/arch/mips32/include/arch/barrier.h ) (1 diff)

kernel/arch/sparc64/src/smc.c

@@ -27 +27 @@
  */
 
-/** @addtogroup mips32
- * @{
- */
-/** @file
- */
+#include <barrier.h>
+#include <arch/barrier.h>
 
-#ifndef KERN_mips32_BARRIER_H_
-#define KERN_mips32_BARRIER_H_
+#if defined(US)
 
-/*
- * TODO: implement true MIPS memory barriers for macros below.
- */
-#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
-#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
+#define FLUSH_INVAL_MIN  4
 
-#define memory_barrier() asm volatile ("" ::: "memory")
-#define read_barrier()   asm volatile ("" ::: "memory")
-#define write_barrier()  asm volatile ("" ::: "memory")
+void smc_coherence(void *a, size_t l)
+{
+        asm volatile ("membar #StoreStore\n" ::: "memory");
 
-#ifdef KERNEL
+        for (size_t i = 0; i < l; i += FLUSH_INVAL_MIN) {
+                asm volatile (
+                    "flush %[reg]\n"
+                    :: [reg] "r" (a + i)
+                    : "memory"
+                );
+        }
+}
 
-#define smc_coherence(a, l)
+#elif defined (US3)
 
-#endif  /* KERNEL */
 
-#endif
+void smc_coherence(void *a, size_t l)
+{
+        asm volatile ("membar #StoreStore\n" ::: "memory");
 
-/** @}
- */
+        flush_pipeline();
+}
+
+#endif  /* defined(US3) */
+