Changes in kernel/arch/sparc64/src/mm/sun4u/as.c [da1bafb:74cbac7d] in mainline
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kernel/arch/sparc64/src/mm/sun4u/as.c
rda1bafb r74cbac7d 41 41 42 42 #ifdef CONFIG_TSB 43 44 43 #include <arch/mm/tsb.h> 45 44 #include <arch/memstr.h> … … 48 47 #include <bitops.h> 49 48 #include <macros.h> 50 51 49 #endif /* CONFIG_TSB */ 52 50 … … 60 58 } 61 59 62 int as_constructor_arch(as_t *as, unsignedint flags)60 int as_constructor_arch(as_t *as, int flags) 63 61 { 64 62 #ifdef CONFIG_TSB … … 66 64 * The order must be calculated with respect to the emulated 67 65 * 16K page size. 68 * 69 */ 70 uint8_t order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * 66 */ 67 int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * 71 68 sizeof(tsb_entry_t)) >> FRAME_WIDTH); 72 69 73 70 uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); 74 71 75 72 if (!tsb) 76 73 return -1; 77 74 78 75 as->arch.itsb = (tsb_entry_t *) tsb; 79 76 as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * 80 77 sizeof(tsb_entry_t)); 81 78 82 79 memsetb(as->arch.itsb, 83 80 (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0); 84 81 #endif 85 86 82 return 0; 87 83 } … … 97 93 sizeof(tsb_entry_t)) >> FRAME_WIDTH; 98 94 frame_free(KA2PA((uintptr_t) as->arch.itsb)); 99 100 95 return cnt; 101 96 #else … … 104 99 } 105 100 106 int as_create_arch(as_t *as, unsignedint flags)101 int as_create_arch(as_t *as, int flags) 107 102 { 108 103 #ifdef CONFIG_TSB 109 104 tsb_invalidate(as, 0, (size_t) -1); 110 105 #endif 111 112 106 return 0; 113 107 } … … 129 123 * 130 124 * Moreover, the as->asid is protected by asidlock, which is being held. 131 *132 125 */ 133 126 … … 137 130 * secondary context register from the TL=1 code just before switch to 138 131 * userspace. 139 *140 132 */ 141 133 ctx.v = 0; 142 134 ctx.context = as->asid; 143 135 mmu_secondary_context_write(ctx.v); 144 145 #ifdef CONFIG_TSB 136 137 #ifdef CONFIG_TSB 146 138 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); 147 139 148 140 ASSERT(as->arch.itsb && as->arch.dtsb); 149 141 150 142 uintptr_t tsb = (uintptr_t) as->arch.itsb; 151 143 152 144 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { 153 145 /* … … 155 147 * by the locked 4M kernel DTLB entry. We need 156 148 * to map both TSBs explicitly. 157 *158 149 */ 159 150 dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb); 160 151 dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true); 161 152 } 162 153 163 154 /* 164 155 * Setup TSB Base registers. 165 *166 156 */ 167 157 tsb_base_reg_t tsb_base; 168 158 169 159 tsb_base.value = 0; 170 160 tsb_base.size = TSB_SIZE; 171 161 tsb_base.split = 0; 172 162 173 163 tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH; 174 164 itsb_base_write(tsb_base.value); … … 185 175 * Clearing the extension registers will ensure that the value of the 186 176 * TSB Base register will be used as an address of TSB, making the code 187 * compatible with the US port. 188 * 177 * compatible with the US port. 189 178 */ 190 179 itsb_primary_extension_write(0); … … 206 195 void as_deinstall_arch(as_t *as) 207 196 { 197 208 198 /* 209 199 * Note that we don't and may not lock the address space. That's ok … … 211 201 * 212 202 * Moreover, the as->asid is protected by asidlock, which is being held. 213 * 214 */ 215 203 */ 204 216 205 #ifdef CONFIG_TSB 217 206 uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); 218 207 219 208 ASSERT(as->arch.itsb && as->arch.dtsb); 220 209 221 210 uintptr_t tsb = (uintptr_t) as->arch.itsb; 222 211 223 212 if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { 224 213 /*
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