Changeset 75e1db0 in mainline


Ignore:
Timestamp:
2005-12-19T22:41:07Z (19 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d6e8529
Parents:
031e264
Message:

sparc64 work.
Implement interrupt_disable(), interrupt_enable(), interrupt_restore() and interrupt_read() functions.
Fix context save/restore to save/restore register %i7.

Files:
8 edited

Legend:

Unmodified
Added
Removed

  • arch/sparc64/include/asm.h

    r031e264 r75e1db0  
    3030#define __sparc64_ASM_H__
    3131
     32#include <typedefs.h>
    3233#include <arch/types.h>
     34#include <arch/register.h>
    3335#include <config.h>
     36
     37/** Read Processor State register.
     38 *
     39 * @return Value of PSTATE register.
     40 */
     41static inline __u64 pstate_read(void)
     42{
     43        __u64 v;
     44       
     45        __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
     46       
     47        return v;
     48}
     49
     50/** Write Processor State register.
     51 *
     52 * @param New value of PSTATE register.
     53 */
     54static inline void pstate_write(__u64 v)
     55{
     56        __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
     57}
     58
    3459
    3560/** Enable interrupts.
    … …  
    4166 */
    4267static inline ipl_t interrupts_enable(void) {
     68        pstate_reg_t pstate;
     69        __u64 value;
     70       
     71        value = pstate_read();
     72        pstate.value = value;
     73        pstate.ie = true;
     74        pstate_write(pstate.value);
     75       
     76        return (ipl_t) value;
    4377}
    4478
    … …  
    5185 */
    5286static inline ipl_t interrupts_disable(void) {
     87        pstate_reg_t pstate;
     88        __u64 value;
     89       
     90        value = pstate_read();
     91        pstate.value = value;
     92        pstate.ie = false;
     93        pstate_write(pstate.value);
     94       
     95        return (ipl_t) value;
    5396}
    5497
    … …  
    60103 */
    61104static inline void interrupts_restore(ipl_t ipl) {
     105        pstate_reg_t pstate;
     106       
     107        pstate.value = pstate_read();
     108        pstate.ie = ((pstate_reg_t) ipl).ie;
     109        pstate_write(pstate.value);
    62110}
    63111
    … …  
    69117 */
    70118static inline ipl_t interrupts_read(void) {
     119        return (ipl_t) pstate_read();
    71120}
    72121
    … …  
    81130        __address v;
    82131       
    83         __asm__ volatile ("and %%o6, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
     132        __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    84133       
    85134        return v;

  • arch/sparc64/include/context.h

    r031e264 r75e1db0  
    6767        __address sp;           /* %o6 */
    6868        __address pc;           /* %o7 */
    69         __address fp;
     69        __address fp;           /* %i6 */
     70        __address i7;
    7071        ipl_t ipl;
    7172};

  • arch/sparc64/include/context_offset.h

    r031e264 r75e1db0  
    99#define OFFSET_PC  0x30
    1010#define OFFSET_FP  0x38
     11#define OFFSET_I7  0x40

  • arch/sparc64/include/register.h

    r031e264 r75e1db0  
    4747typedef union ver_reg ver_reg_t;
    4848
     49/** Processor State Register. */
     50union pstate_reg {
     51        __u64 value;
     52        struct {
     53                __u64 : 52;
     54                unsigned ig : 1;        /**< Interrupt Globals. */
     55                unsigned mg : 1;        /**< MMU Globals. */
     56                unsigned cle : 1;       /**< Current Little Endian. */
     57                unsigned tle : 1;       /**< Trap Little Endian. */
     58                unsigned mm : 2;        /**< Memory Model. */
     59                unsigned red : 1;       /**< RED state. */
     60                unsigned pef : 1;       /**< Enable floating-point. */
     61                unsigned am : 1;        /**< 32-bit Address Mask. */
     62                unsigned priv : 1;      /**< Privileged Mode. */
     63                unsigned ie : 1;        /**< Interrupt Enable. */
     64                unsigned ag : 1;        /**< Alternate Globals*/
     65        } __attribute__ ((packed));
     66};
     67typedef union pstate_reg pstate_reg_t;
     68
    4969#endif

  • arch/sparc64/src/context.S

    r031e264 r75e1db0  
    5252        stx %sp, [\r + OFFSET_SP]
    5353        stx %fp, [\r + OFFSET_FP]
     54        stx %i7, [\r + OFFSET_I7]
    5455.endm
    5556
    … …  
    6364        ldx [\r + OFFSET_SP], %sp
    6465        ldx [\r + OFFSET_FP], %fp
     66        ldx [\r + OFFSET_I7], %i7
    6567.endm
    6668

  • arch/sparc64/src/dummy.s

    r031e264 r75e1db0  
    5959userspace:
    6060
    61 
    6261dummy:
    63 0:
    6462        retl
    6563        nop

  • generic/include/debug.h

    r031e264 r75e1db0  
    5151 */
    5252#ifdef CONFIG_DEBUG
    53 #       define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s)", #expr); }
     53#       define ASSERT(expr) if (!(expr)) { panic("assertion failed (%s), caller=%P\n", #expr, CALLER); }
    5454#else
    5555#       define ASSERT(expr)

  • generic/src/proc/scheduler.c

    r031e264 r75e1db0  
    295295
    296296                        spinlock_lock(&CPU->lock);
    297                         if(CPU->fpu_owner==THREAD) CPU->fpu_owner=NULL;
     297                        if(CPU->fpu_owner==THREAD)
     298                                CPU->fpu_owner=NULL;
    298299                        spinlock_unlock(&CPU->lock);
    299300
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