Changeset 771cd22 in mainline for kernel/arch/sparc64/src/mm/tsb.c


Ignore:
Timestamp:
2006-12-16T19:07:02Z (18 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
7e7c8747
Parents:
1ecdbb0
Message:

Formatting and indentation changes.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/sparc64/src/mm/tsb.c

    r1ecdbb0 r771cd22  
    4242#include <debug.h>
    4343
    44 #define TSB_INDEX_MASK          ((1<<(21+1+TSB_SIZE-PAGE_WIDTH))-1)
     44#define TSB_INDEX_MASK          ((1 << (21 + 1 + TSB_SIZE - PAGE_WIDTH)) - 1)
    4545
    4646/** Invalidate portion of TSB.
    4747 *
    48  * We assume that the address space is already locked.
    49  * Note that respective portions of both TSBs
    50  * are invalidated at a time.
     48 * We assume that the address space is already locked. Note that respective
     49 * portions of both TSBs are invalidated at a time.
    5150 *
    5251 * @param as Address space.
    5352 * @param page First page to invalidate in TSB.
    54  * @param pages Number of pages to invalidate.
    55  *              Value of (count_t) -1 means the whole TSB.
     53 * @param pages Number of pages to invalidate. Value of (count_t) -1 means the
     54 *      whole TSB.
    5655 */
    5756void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
     
    6665       
    6766        for (i = 0; i < cnt; i++) {
    68                 as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true;
    69                 as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true;
     67                as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
     68                        true;
     69                as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
     70                        true;
    7071        }
    7172}
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