Changes in kernel/arch/ia64/include/asm.h [dbd5df1b:7a0359b] in mainline
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kernel/arch/ia64/include/asm.h (modified) (27 diffs)
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kernel/arch/ia64/include/asm.h
rdbd5df1b r7a0359b 40 40 #include <typedefs.h> 41 41 #include <arch/register.h> 42 #include <trace.h> 42 43 43 44 #define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL 44 45 45 static inline void pio_write_8(ioport8_t *port, uint8_t v)46 NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) 46 47 { 47 48 uintptr_t prt = (uintptr_t) port; … … 56 57 } 57 58 58 static inline void pio_write_16(ioport16_t *port, uint16_t v)59 NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) 59 60 { 60 61 uintptr_t prt = (uintptr_t) port; … … 69 70 } 70 71 71 static inline void pio_write_32(ioport32_t *port, uint32_t v)72 NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) 72 73 { 73 74 uintptr_t prt = (uintptr_t) port; … … 82 83 } 83 84 84 static inline uint8_t pio_read_8(ioport8_t *port)85 NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) 85 86 { 86 87 uintptr_t prt = (uintptr_t) port; … … 95 96 } 96 97 97 static inline uint16_t pio_read_16(ioport16_t *port)98 NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) 98 99 { 99 100 uintptr_t prt = (uintptr_t) port; … … 108 109 } 109 110 110 static inline uint32_t pio_read_32(ioport32_t *port)111 NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) 111 112 { 112 113 uintptr_t prt = (uintptr_t) port; … … 126 127 * The stack is assumed to be STACK_SIZE long. 127 128 * The stack must start on page boundary. 128 */ 129 static inline uintptr_t get_stack_base(void) 130 { 131 uint64_t v; 132 133 /* I'm not sure why but this code bad inlines in scheduler, 134 so THE shifts about 16B and causes kernel panic 135 136 asm volatile ( 137 "and %[value] = %[mask], r12" 138 : [value] "=r" (v) 139 : [mask] "r" (~(STACK_SIZE - 1)) 140 ); 141 return v; 142 143 This code have the same meaning but inlines well. 144 */ 129 * 130 */ 131 NO_TRACE static inline uintptr_t get_stack_base(void) 132 { 133 uint64_t v; 134 135 /* 136 * I'm not sure why but this code inlines badly 137 * in scheduler, resulting in THE shifting about 138 * 16B and causing kernel panic. 139 * 140 * asm volatile ( 141 * "and %[value] = %[mask], r12" 142 * : [value] "=r" (v) 143 * : [mask] "r" (~(STACK_SIZE - 1)) 144 * ); 145 * return v; 146 * 147 * The following code has the same semantics but 148 * inlines correctly. 149 * 150 */ 145 151 146 152 asm volatile ( … … 155 161 * 156 162 * @return PSR. 157 */ 158 static inline uint64_t psr_read(void) 163 * 164 */ 165 NO_TRACE static inline uint64_t psr_read(void) 159 166 { 160 167 uint64_t v; … … 171 178 * 172 179 * @return Return location of interruption vector table. 173 */ 174 static inline uint64_t iva_read(void) 180 * 181 */ 182 NO_TRACE static inline uint64_t iva_read(void) 175 183 { 176 184 uint64_t v; … … 187 195 * 188 196 * @param v New location of interruption vector table. 189 */ 190 static inline void iva_write(uint64_t v) 197 * 198 */ 199 NO_TRACE static inline void iva_write(uint64_t v) 191 200 { 192 201 asm volatile ( … … 196 205 } 197 206 198 199 207 /** Read IVR (External Interrupt Vector Register). 200 208 * 201 * @return Highest priority, pending, unmasked external interrupt vector. 202 */ 203 static inline uint64_t ivr_read(void) 209 * @return Highest priority, pending, unmasked external 210 * interrupt vector. 211 * 212 */ 213 NO_TRACE static inline uint64_t ivr_read(void) 204 214 { 205 215 uint64_t v; … … 213 223 } 214 224 215 static inline uint64_t cr64_read(void)225 NO_TRACE static inline uint64_t cr64_read(void) 216 226 { 217 227 uint64_t v; … … 225 235 } 226 236 227 228 237 /** Write ITC (Interval Timer Counter) register. 229 238 * 230 239 * @param v New counter value. 231 */ 232 static inline void itc_write(uint64_t v) 240 * 241 */ 242 NO_TRACE static inline void itc_write(uint64_t v) 233 243 { 234 244 asm volatile ( … … 241 251 * 242 252 * @return Current counter value. 243 */ 244 static inline uint64_t itc_read(void) 253 * 254 */ 255 NO_TRACE static inline uint64_t itc_read(void) 245 256 { 246 257 uint64_t v; … … 257 268 * 258 269 * @param v New match value. 259 */ 260 static inline void itm_write(uint64_t v) 270 * 271 */ 272 NO_TRACE static inline void itm_write(uint64_t v) 261 273 { 262 274 asm volatile ( … … 269 281 * 270 282 * @return Match value. 271 */ 272 static inline uint64_t itm_read(void) 283 * 284 */ 285 NO_TRACE static inline uint64_t itm_read(void) 273 286 { 274 287 uint64_t v; … … 285 298 * 286 299 * @return Current vector and mask bit. 287 */ 288 static inline uint64_t itv_read(void) 300 * 301 */ 302 NO_TRACE static inline uint64_t itv_read(void) 289 303 { 290 304 uint64_t v; … … 301 315 * 302 316 * @param v New vector and mask bit. 303 */ 304 static inline void itv_write(uint64_t v) 317 * 318 */ 319 NO_TRACE static inline void itv_write(uint64_t v) 305 320 { 306 321 asm volatile ( … … 313 328 * 314 329 * @param v This value is ignored. 315 */ 316 static inline void eoi_write(uint64_t v) 330 * 331 */ 332 NO_TRACE static inline void eoi_write(uint64_t v) 317 333 { 318 334 asm volatile ( … … 325 341 * 326 342 * @return Current value of TPR. 327 */ 328 static inline uint64_t tpr_read(void) 343 * 344 */ 345 NO_TRACE static inline uint64_t tpr_read(void) 329 346 { 330 347 uint64_t v; … … 341 358 * 342 359 * @param v New value of TPR. 343 */ 344 static inline void tpr_write(uint64_t v) 360 * 361 */ 362 NO_TRACE static inline void tpr_write(uint64_t v) 345 363 { 346 364 asm volatile ( … … 356 374 * 357 375 * @return Old interrupt priority level. 358 */ 359 static ipl_t interrupts_disable(void) 376 * 377 */ 378 NO_TRACE static ipl_t interrupts_disable(void) 360 379 { 361 380 uint64_t v; … … 377 396 * 378 397 * @return Old interrupt priority level. 379 */ 380 static ipl_t interrupts_enable(void) 398 * 399 */ 400 NO_TRACE static ipl_t interrupts_enable(void) 381 401 { 382 402 uint64_t v; … … 399 419 * 400 420 * @param ipl Saved interrupt priority level. 401 */ 402 static inline void interrupts_restore(ipl_t ipl) 421 * 422 */ 423 NO_TRACE static inline void interrupts_restore(ipl_t ipl) 403 424 { 404 425 if (ipl & PSR_I_MASK) … … 411 432 * 412 433 * @return PSR. 413 */ 414 static inline ipl_t interrupts_read(void) 434 * 435 */ 436 NO_TRACE static inline ipl_t interrupts_read(void) 415 437 { 416 438 return (ipl_t) psr_read(); … … 422 444 * 423 445 */ 424 static inline bool interrupts_disabled(void)446 NO_TRACE static inline bool interrupts_disabled(void) 425 447 { 426 448 return !(psr_read() & PSR_I_MASK); … … 428 450 429 451 /** Disable protection key checking. */ 430 static inline void pk_disable(void)452 NO_TRACE static inline void pk_disable(void) 431 453 { 432 454 asm volatile (
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