Changes in kernel/arch/mips32/include/mm/tlb.h [e2d97d7:7a0359b] in mainline

File:

• kernel/arch/mips32/include/mm/tlb.h (modified) (9 diffs)

kernel/arch/mips32/include/mm/tlb.h

@@ -36 +36 @@
 #define KERN_mips32_TLB_H_
 
-#include <arch/types.h>
 #include <typedefs.h>
 #include <arch/mm/asid.h>
 #include <arch/exception.h>
+#include <trace.h>
 
 #define TLB_ENTRY_COUNT  48
@@ -59 +59 @@
 typedef union {
         struct {
-#ifdef BIG_ENDIAN
+#ifdef __BE__
                 unsigned : 2;       /* zero */
                 unsigned pfn : 24;  /* frame number */
@@ -80 +80 @@
 typedef union {
         struct {
-#ifdef BIG_ENDIAN
+#ifdef __BE__
                 unsigned vpn2 : 19;
                 unsigned : 5;
@@ -95 +95 @@
 typedef union {
         struct {
-#ifdef BIG_ENDIAN
+#ifdef __BE__
                 unsigned : 7;
                 unsigned mask : 12;
@@ -110 +110 @@
 typedef union {
         struct {
-#ifdef BIG_ENDIAN
+#ifdef __BE__
                 unsigned p : 1;
                 unsigned : 27;
@@ -127 +127 @@
  * Probe TLB for Matching Entry.
  */
-static inline void tlbp(void)
+NO_TRACE static inline void tlbp(void)
 {
         asm volatile ("tlbp\n\t");
@@ -137 +137 @@
  * Read Indexed TLB Entry.
  */
-static inline void tlbr(void)
+NO_TRACE static inline void tlbr(void)
 {
         asm volatile ("tlbr\n\t");
@@ -146 +146 @@
  * Write Indexed TLB Entry.
  */
-static inline void tlbwi(void)
+NO_TRACE static inline void tlbwi(void)
 {
         asm volatile ("tlbwi\n\t");
@@ -155 +155 @@
  * Write Random TLB Entry.
  */
-static inline void tlbwr(void)
+NO_TRACE static inline void tlbwr(void)
 {
         asm volatile ("tlbwr\n\t");