Changes in kernel/arch/ppc32/include/asm.h [d99c1d2:7a0359b] in mainline
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kernel/arch/ppc32/include/asm.h
rd99c1d2 r7a0359b 38 38 #include <typedefs.h> 39 39 #include <config.h> 40 #include <arch/cpu.h> 41 #include <arch/mm/asid.h> 42 #include <trace.h> 43 44 NO_TRACE static inline uint32_t msr_read(void) 45 { 46 uint32_t msr; 47 48 asm volatile ( 49 "mfmsr %[msr]\n" 50 : [msr] "=r" (msr) 51 ); 52 53 return msr; 54 } 55 56 NO_TRACE static inline void msr_write(uint32_t msr) 57 { 58 asm volatile ( 59 "mtmsr %[msr]\n" 60 :: [msr] "r" (msr) 61 ); 62 } 63 64 NO_TRACE static inline void sr_set(uint32_t flags, asid_t asid, uint32_t sr) 65 { 66 asm volatile ( 67 "mtsrin %[value], %[sr]\n" 68 :: [value] "r" ((flags << 16) + (asid << 4) + sr), 69 [sr] "r" (sr << 28) 70 ); 71 } 72 73 NO_TRACE static inline uint32_t sr_get(uint32_t vaddr) 74 { 75 uint32_t vsid; 76 77 asm volatile ( 78 "mfsrin %[vsid], %[vaddr]\n" 79 : [vsid] "=r" (vsid) 80 : [vaddr] "r" (vaddr) 81 ); 82 83 return vsid; 84 } 85 86 NO_TRACE static inline uint32_t sdr1_get(void) 87 { 88 uint32_t sdr1; 89 90 asm volatile ( 91 "mfsdr1 %[sdr1]\n" 92 : [sdr1] "=r" (sdr1) 93 ); 94 95 return sdr1; 96 } 40 97 41 98 /** Enable interrupts. … … 45 102 * 46 103 * @return Old interrupt priority level. 47 */ 48 static inline ipl_t interrupts_enable(void) 49 { 50 ipl_t v; 51 ipl_t tmp; 52 53 asm volatile ( 54 "mfmsr %0\n" 55 "mfmsr %1\n" 56 "ori %1, %1, 1 << 15\n" 57 "mtmsr %1\n" 58 : "=r" (v), "=r" (tmp) 59 ); 60 return v; 104 * 105 */ 106 NO_TRACE static inline ipl_t interrupts_enable(void) 107 { 108 ipl_t ipl = msr_read(); 109 msr_write(ipl | MSR_EE); 110 return ipl; 61 111 } 62 112 … … 67 117 * 68 118 * @return Old interrupt priority level. 69 */ 70 static inline ipl_t interrupts_disable(void) 71 { 72 ipl_t v; 73 ipl_t tmp; 74 75 asm volatile ( 76 "mfmsr %0\n" 77 "mfmsr %1\n" 78 "rlwinm %1, %1, 0, 17, 15\n" 79 "mtmsr %1\n" 80 : "=r" (v), "=r" (tmp) 81 ); 82 return v; 119 * 120 */ 121 NO_TRACE static inline ipl_t interrupts_disable(void) 122 { 123 ipl_t ipl = msr_read(); 124 msr_write(ipl & (~MSR_EE)); 125 return ipl; 83 126 } 84 127 … … 88 131 * 89 132 * @param ipl Saved interrupt priority level. 90 */ 91 static inline void interrupts_restore(ipl_t ipl) 92 { 93 ipl_t tmp; 94 95 asm volatile ( 96 "mfmsr %1\n" 97 "rlwimi %0, %1, 0, 17, 15\n" 98 "cmpw 0, %0, %1\n" 99 "beq 0f\n" 100 "mtmsr %0\n" 101 "0:\n" 102 : "=r" (ipl), "=r" (tmp) 103 : "0" (ipl) 104 : "cr0" 105 ); 133 * 134 */ 135 NO_TRACE static inline void interrupts_restore(ipl_t ipl) 136 { 137 msr_write((msr_read() & (~MSR_EE)) | (ipl & MSR_EE)); 106 138 } 107 139 … … 111 143 * 112 144 * @return Current interrupt priority level. 113 */ 114 static inline ipl_t interrupts_read(void) 115 { 116 ipl_t v; 117 118 asm volatile ( 119 "mfmsr %0\n" 120 : "=r" (v) 121 ); 122 return v; 145 * 146 */ 147 NO_TRACE static inline ipl_t interrupts_read(void) 148 { 149 return msr_read(); 150 } 151 152 /** Check whether interrupts are disabled. 153 * 154 * @return True if interrupts are disabled. 155 * 156 */ 157 NO_TRACE static inline bool interrupts_disabled(void) 158 { 159 return ((msr_read() & MSR_EE) == 0); 123 160 } 124 161 … … 128 165 * The stack is assumed to be STACK_SIZE bytes long. 129 166 * The stack must start on page boundary. 130 */ 131 static inline uintptr_t get_stack_base(void) 132 { 133 uintptr_t v; 134 135 asm volatile ( 136 "and %0, %%sp, %1\n" 137 : "=r" (v) 138 : "r" (~(STACK_SIZE - 1)) 139 ); 140 return v; 141 } 142 143 static inline void cpu_sleep(void) 144 { 167 * 168 */ 169 NO_TRACE static inline uintptr_t get_stack_base(void) 170 { 171 uintptr_t base; 172 173 asm volatile ( 174 "and %[base], %%sp, %[mask]\n" 175 : [base] "=r" (base) 176 : [mask] "r" (~(STACK_SIZE - 1)) 177 ); 178 179 return base; 180 } 181 182 NO_TRACE static inline void cpu_sleep(void) 183 { 184 } 185 186 NO_TRACE static inline void pio_write_8(ioport8_t *port, uint8_t v) 187 { 188 *port = v; 189 } 190 191 NO_TRACE static inline void pio_write_16(ioport16_t *port, uint16_t v) 192 { 193 *port = v; 194 } 195 196 NO_TRACE static inline void pio_write_32(ioport32_t *port, uint32_t v) 197 { 198 *port = v; 199 } 200 201 NO_TRACE static inline uint8_t pio_read_8(ioport8_t *port) 202 { 203 return *port; 204 } 205 206 NO_TRACE static inline uint16_t pio_read_16(ioport16_t *port) 207 { 208 return *port; 209 } 210 211 NO_TRACE static inline uint32_t pio_read_32(ioport32_t *port) 212 { 213 return *port; 145 214 } 146 215 … … 149 218 extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry); 150 219 151 static inline void pio_write_8(ioport8_t *port, uint8_t v)152 {153 *port = v;154 }155 156 static inline void pio_write_16(ioport16_t *port, uint16_t v)157 {158 *port = v;159 }160 161 static inline void pio_write_32(ioport32_t *port, uint32_t v)162 {163 *port = v;164 }165 166 static inline uint8_t pio_read_8(ioport8_t *port)167 {168 return *port;169 }170 171 static inline uint16_t pio_read_16(ioport16_t *port)172 {173 return *port;174 }175 176 static inline uint32_t pio_read_32(ioport32_t *port)177 {178 return *port;179 }180 181 220 #endif 182 221
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