Changeset 7bb6b06 in mainline for kernel/arch/sparc64/src/start.S

Timestamp:

2006-09-10T21:21:39Z (19 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9a5b556

Parents:

208fa65

Message:

Small improvements here and there.

File:

• kernel/arch/sparc64/src/start.S (modified) (6 diffs)

kernel/arch/sparc64/src/start.S

@@ -77 +77 @@
         mov %o1, %o2
         mov %o0, %o1
-        set bootinfo, %o0
+        sethi %hi(bootinfo), %o0
         call memcpy
-        nop
+        or %o0, %lo(bootinfo), %o0
 
         /*
          * Switch to kernel trap table.
          */
-        set trap_table, %g1
-        wrpr %g1, 0, %tba
+        sethi %hi(trap_table), %g1
+        wrpr %g1, %lo(trap_table), %tba
 
         /* 
@@ -121 +121 @@
         sllx %r2, TTE_SIZE_SHIFT, %r2; \
         or %r1, %r2, %r1; \
-        set 1, %r2; \
+        mov 1, %r2; \
         sllx %r2, TTE_V_SHIFT, %r2; \
         or %r1, %r2, %r1;
@@ -173 +173 @@
         ! write ITLB tag of context 1
         SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
-        set VA_DMMU_TAG_ACCESS, %g2
+        mov VA_DMMU_TAG_ACCESS, %g2
         stxa %g1, [%g2] ASI_IMMU
         flush %g5
@@ -183 +183 @@
         
         ! switch to context 1
-        set MEM_CONTEXT_TEMP, %g1
+        mov MEM_CONTEXT_TEMP, %g1
         stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
         flush %g5
@@ -194 +194 @@
         ! write ITLB tag of context 0
         SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL)
-        set VA_DMMU_TAG_ACCESS, %g2
+        mov VA_DMMU_TAG_ACCESS, %g2
         stxa %g1, [%g2] ASI_IMMU
         flush %g5
@@ -211 +211 @@
 
         ! set context 1 in the primary context register
-        set MEM_CONTEXT_TEMP, %g1
+        mov MEM_CONTEXT_TEMP, %g1
         stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
         flush %g5