Changeset 7be6379 in mainline

Timestamp:

2013-02-06T08:00:50Z (12 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

d5b9e8d

Parents:

b5e17b1

Message:

Handle only unmasked pending interrupts.

Location:

kernel/arch/mips32

Files:

• include/cp0.h (modified) (1 diff)
• src/exception.c (modified) (1 diff)

kernel/arch/mips32/include/cp0.h

@@ -45 +45 @@
 #define cp0_status_im_shift  8
 #define cp0_status_im_mask   0xff00
+
+#define cp0_cause_ip_shift  8
+#define cp0_cause_ip_mask   0xff00
 
 #define cp0_cause_excno(cause)   ((cause >> 2) & 0x1f)

kernel/arch/mips32/src/exception.c

@@ -165 +165 @@
 static void interrupt_exception(unsigned int n, istate_t *istate)
 {
+        uint32_t ip;
+        uint32_t im;
+
         /* Decode interrupt number and process the interrupt */
-        uint32_t cause = (cp0_cause_read() >> 8) & 0xff;
+        ip = (cp0_cause_read() & cp0_cause_ip_mask) >> cp0_cause_ip_shift;
+        im = (cp0_status_read() & cp0_status_im_mask) >> cp0_status_im_shift;
         
         unsigned int i;
         for (i = 0; i < 8; i++) {
-                if (cause & (1 << i)) {
+
+                /*
+                 * The interrupt could only occur if it is unmasked in the
+                 * status register. On the other hand, an interrupt can be
+                 * apparently pending even if it is masked, so we need to
+                 * check both the masked and pending interrupts.
+                 */
+                if (im & ip & (1 << i)) {
                         irq_t *irq = irq_dispatch_and_lock(i);
                         if (irq) {