Changeset 7bf9217 in mainline

Timestamp:

2013-08-08T20:59:02Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e93bb24

Parents:

15187c3

Message:

armv7: Enable Write back write allocate caches.

Files:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)
• kernel/arch/arm32/include/arch/mm/page.h (modified) (1 diff)
• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -147 +147 @@
          * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
          */
-        //TODO: Use write-back write-allocate caches
-        pte->tex = section_cacheable(frame) ? 6 : 0;
-        pte->bufferable = section_cacheable(frame) ? 0 : 0;
-        pte->cacheable = section_cacheable(frame) ? 1 : 0;
+        pte->tex = section_cacheable(frame) ? 5 : 0;
+        pte->cacheable = section_cacheable(frame) ? 0 : 0;
+        pte->bufferable = section_cacheable(frame) ? 1 : 0;
 #else
         pte->bufferable = 1;
@@ -184 +183 @@
          */
         uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
-        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
         TTBR0_write(val);
 }

kernel/arch/arm32/include/arch/mm/page.h

@@ -154 +154 @@
 {
         uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
-        val |= TTBR_RGN_WT_CACHE | TTBR_C_FLAG;
+        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
         TTBR0_write(val);
 }

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -265 +265 @@
                  * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
                  */
-                //TODO: Use writeback, write-allocate caches
-                p->tex = 6;
-                p->cacheable = 1;
-                p->bufferable = 0;
+                p->tex = 5;
+                p->cacheable = 0;
+                p->bufferable = 1;
         } else {
                 /*