Changeset 7c322bd in mainline

Timestamp:

2006-03-12T13:13:12Z (19 years ago)

Author:

Jakub Vana <jakub.vana@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bdab828

Parents:

e792fa7

Message:

Itanium tlb_invalidate_all

Files:

• arch/ia64/include/pal/pal.h (modified) (1 diff)
• arch/ia64/src/mm/tlb.c (modified) (2 diffs)
• kernel.config (modified) (1 diff)
• test/mm/purge1/test.c (added)

arch/ia64/include/pal/pal.h

@@ -89 +89 @@
 #define PAL_PMI_ENTRYPOINT      32
 
+/*
+        Ski PTCE data
+*/
+#define PAL_PTCE_INFO_BASE() (0x100000000LL)
+#define PAL_PTCE_INFO_COUNT1() (2)
+#define PAL_PTCE_INFO_COUNT2() (3)
+#define PAL_PTCE_INFO_STRIDE1() (0x10000000)
+#define PAL_PTCE_INFO_STRIDE2() (0x2000)
+
+
 #endif

arch/ia64/src/mm/tlb.c

@@ -39 +39 @@
 #include <arch/barrier.h>
 #include <arch/interrupt.h>
+#include <arch/pal/pal.h>
+#include <arch/asm.h>
 #include <typedefs.h>
 #include <panic.h>
@@ -46 +48 @@
 void tlb_invalidate_all(void)
 {
-        /* TODO */
+                __address adr;
+                __u32 count1,count2,stride1,stride2;
+                
+                int i,j;
+                
+                adr=PAL_PTCE_INFO_BASE();
+                count1=PAL_PTCE_INFO_COUNT1();
+                count2=PAL_PTCE_INFO_COUNT2();
+                stride1=PAL_PTCE_INFO_STRIDE1();
+                stride2=PAL_PTCE_INFO_STRIDE2();
+                
+                interrupts_disable();
+
+                for(i=0;i<count1;i++)
+                {
+                        for(j=0;j<count2;j++)
+                        {
+                                asm volatile
+                                (
+                                        "ptc.e %0;;"
+                                        :
+                                        :"r" (adr)
+                                );
+                                adr+=stride2;
+                        }
+                        adr+=stride1;
+                }
+
+                interrupts_enable();
+
+                srlz_d();
+                srlz_i();
 }
 

kernel.config

@@ -90 +90 @@
 @ "mm/slab2" SLAB test2 - SMP CPU cache
 @ "fault/fault1" Write to NULL (maybe page fault)
+@ "mm/purge1" Itanium TLB purge test
 @ [ARCH=mips32] "debug/mips1" Mips breakpoint-debug test 
 ! CONFIG_TEST (choice)