Changeset 7cd7a8d in mainline for kernel/arch/ia64/src/fpu_context.c

Timestamp:

2018-08-02T20:38:05Z (6 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

9b7adc38

Parents:

0c27956

git-author:

Jakub Jermar <jakub@…> (2018-08-01 22:48:10)

git-committer:

Jakub Jermar <jakub@…> (2018-08-02 20:38:05)

Message:

Preserve AR.FPSR in thread context

AR.FPSR is a preserved register so it should be part of the thread
context, leaving its extra copy in istate_t rather for debugging
purposes.

In this commit we also disable all IEEE FP traps and the
Denormal/Unnormal Operand Floating-Point Exception fault for each new
thread context, leaving the thread with the possibility to change this
setting later in uspace.

File:

• kernel/arch/ia64/src/fpu_context.c (modified) (4 diffs)

kernel/arch/ia64/src/fpu_context.c

@@ -462 +462 @@
 void fpu_enable(void)
 {
-        uint64_t a = 0;
-
         asm volatile (
             "rsm %0 ;;"
@@ -471 +469 @@
             : "i" (PSR_DFH_MASK)
         );
-
-        asm volatile (
-            "mov %0 = ar.fpsr ;;\n"
-            "or %0 = %0,%1 ;;\n"
-            "mov ar.fpsr = %0 ;;\n"
-            : "+r" (a)
-            : "r" (0x38)
-        );
 }
 
 void fpu_disable(void)
 {
-        uint64_t a = 0;
-
         asm volatile (
             "ssm %0 ;;\n"
@@ -492 +480 @@
             : "i" (PSR_DFH_MASK)
         );
+}
+
+void fpu_init(void)
+{
+        uint64_t a = 0;
 
         asm volatile (
@@ -498 +491 @@
             "mov ar.fpsr = %0 ;;\n"
             : "+r" (a)
-            : "r" (0x38)
-        );
-}
-
-void fpu_init(void)
-{
-        uint64_t a = 0;
-
-        asm volatile (
-            "mov %0 = ar.fpsr ;;\n"
-            "or %0 = %0,%1 ;;\n"
-            "mov ar.fpsr = %0 ;;\n"
-            : "+r" (a)
-            : "r" (0x38)
+            : "r" (FPSR_TRAPS_ALL)
         );