Changes in kernel/arch/arm32/include/barrier.h [2a8f38a:7dc8bf1] in mainline

File:

• kernel/arch/arm32/include/barrier.h (modified) (3 diffs)

kernel/arch/arm32/include/barrier.h

@@ -39 +39 @@
 /*
  * TODO: implement true ARM memory barriers for macros below.
+ * ARMv6 introduced user access of the following commands:
+ * • Prefetch flush
+ * • Data synchronization barrier
+ * • Data memory barrier
+ * • Clean and prefetch range operations.
+ * ARM Architecture Reference Manual version I ch. B.3.2.1 p. B3-4
  */
 #define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
@@ -54 +60 @@
 #define read_barrier()    asm volatile ("dsb" ::: "memory")
 #define write_barrier()   asm volatile ("dsb st" ::: "memory")
-#elif defined PROCESSOR_ARCH_armv6
-/* ARMv6- use system control coprocessor (CP15) for memory barrier instructions.
- * Although at least mcr p15, 0, r0, c7, c10, 4 is mentioned in earlier archs,
- * CP15 implementation is mandatory only for armv6+.
- */
-#define memory_barrier()  asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 5" ::: "r0", "memory")
-#define read_barrier()    asm volatile ("ldr r0, =0\nmcr p15, 0, r0, c7, c10, 4" ::: "r0", "memory")
-#define write_barrier()   read_barrier()
 #else
-/* Older manuals mention syscalls as a way to implement cache coherency and
- * barriers. See for example ARM Architecture Reference Manual Version D
- * chapter 2.7.4 Prefetching and self-modifying code (p. A2-28)
- */
-// TODO implement on per PROCESSOR basis
 #define memory_barrier()  asm volatile ("" ::: "memory")
 #define read_barrier()    asm volatile ("" ::: "memory")
 #define write_barrier()   asm volatile ("" ::: "memory")
 #endif
-
 /*
  * There are multiple ways ICache can be implemented on ARM machines. Namely
@@ -88 +80 @@
  */
 
-/* Available on both all supported arms,
+#ifdef PROCESSOR_ARCH_armv7_a
+#define smc_coherence(a) asm volatile ( "isb" ::: "memory")
+#define smc_coherence_block(a, l) smc_coherence(a)
+#else
+/* Available on all supported arms,
  * invalidates entire ICache so the written value does not matter. */
+//TODO might be PL1 only on armv5 -
 #define smc_coherence(a) asm volatile ( "mcr p15, 0, r0, c7, c5, 0")
 #define smc_coherence_block(a, l) smc_coherence(a)
+#endif