Changeset 7eb49f4 in mainline

Timestamp:

2012-10-12T21:29:35Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

e2a6b72

Parents:

7290ca0

Message:

rootamdm37x: Set DPLL 3 and 4 to automatic too.

File:

• uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c (modified) (2 diffs)

uspace/drv/infrastructure/rootamdm37x/rootamdm37x.c

@@ -153 +153 @@
         assert(clock_control_cm);
 
-        /* Always set DPLL5 to automatic */
-        uint32_t reg = clock_control_cm->autoidle2_pll;
+        uint32_t reg;
+
+        /* Set DPLL3 and DPLL4 to automatic */
+        reg = clock_control_cm->autoidle_pll;
+        reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_MASK <<
+            CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_SHIFT);
+        reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_MASK <<
+            CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_SHIFT);
+        reg |= (CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_AUTOMATIC <<
+            CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_CORE_DPLL_SHIFT);
+        reg |= (CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_AUTOMATIC <<
+            CLOCK_CONTROL_CM_AUTOIDLE_PLL_AUTO_PERIPH_DPLL_SHIFT);
+        clock_control_cm->autoidle_pll = reg;
+
+        /* Set DPLL5 to automatic */
+        reg = clock_control_cm->autoidle2_pll;
         reg &= ~(CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_MASK <<
             CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_SHIFT);
@@ -160 +174 @@
             CLOCK_CONTROL_CM_AUTOIDLE2_PLL_AUTO_PERIPH2_DPLL_SHIFT);
         clock_control_cm->autoidle2_pll = reg;
+
 
 #ifdef DEBUG_CM